JEDAT Inc.

FineQap

FineVolt

FineArts

FineResQ

Fine Pattern Design Solution

DAC Designer Track

Designer Track in DAC2017

Resistance Driven Routing Methodology of Power Supply Network for Low Power and Multiple Voltage Design

We propose net based power and signal routing methodology which can reduce chip size in more than 10 multi voltage design.
This automatic function can also reduce the routing period 10 times faster compared with manual editing.

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DESIGN/IP TRACK POSTER SESSION in DAC 2016

DESIGN/IP TRACK POSTER SESSION in DAC 2016
“PLL design using automatic analog migration tool”

This slide shows the case study of RVT local circuit optimization for Charge Pump to improve PLL designs.

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DAC2015 DESIGNER TRACK PAPER

DAC2015 DESIGNER TRACK PAPER for Analog circuit design “Circuit Design Method for MOS Analog-Design Reuse” in DAC2015 Designer Track

Diary of a Wimpy Kid: Real Designers Have Strong Methodology which shows automatic circuit migration example with local optimizing methodology. 

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Videos

GT-Router

GT-Router:

Constraint-driven (EM/IR Drop/Noise) power router which minimizes the chip size. Achieved by assigning wire topology and congestion-aware technology including slot insertion.

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PowerVolt

PowerVolt:

Fast power MOS analysis for design optimization and sign off. It allows Static analysis, Dynamic analysis, and Thermal analysis.

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FineArts

FineArts:

Layout editor platform for flat panel display design. It allows reduction of design cycle time and quality improvement by special features.

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Simplify

Simplify:

Auto routing capability for flat panel displays of any shape for mobile/IoT/automotive applications.

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FineAcres/Qap

FineAcres/Qap:

High speed and high accuracy resistance/capacitance extraction tool for long and fat wires between pixels and drivers of flat panel displays.

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FineVolt

FineVolt:

Voltage drop and current density analysis for OLED. The built-in high-speed solver allows verifying the full panel scale data.

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RVT-CircuitSynthesis

RVT-CircuitSynthesis:

Automatically migrates the circuit parameters by device level optimization toward new PDK.

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RVT-LayoutSynthesis

RVT-LayoutSynthesis:

Automatically migrates the layout by extracting the constraint from schematic and layout toward new PDK.

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GT-Router

GT-Router:

The constraint driven custom power line router which can generate reliable and robust slit power line based on the design requirements of each block.

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HOTSCOPE

HOTSCOPE: Net trace and schematic generation

It allows designers to generate the equivalent schematic from the layout data by running equipotential net tracing capabilities. After tracing, it makes possible to provide cross-probing capabilities between schematic and layout.

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HOTSCOPE: 3D

HOTSCOPE: 3D cross-section viewing

After specifying the locations on the layout pattern, 3D structure is displayed and designers can observe the data while rotating in the horizontal and vertical directions. It also allows a variety of analysis functions, such as by the equipotential net tracing and 3D measurement function.

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HOTSCOPE: Resistance

HOTSCOPE: Resistance calculation

>>By specifying the start and end points of the detected net by the net trace function, the designer can easily calculate the parasitic resistance value between the two points.

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DAC Designer Track

GT-Router


Resistance driven routing method” for top level power line routing of the design with low voltage and multi power regions, which enables the reduction of chip area

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RVT-CircuitSynthesis


RVT-CircuitSynthesis, the automatic process migration tool, provides the schematic porting and the parametric circuit optimization between different processes.

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