{"id":14036,"date":"2010-01-07T22:26:00","date_gmt":"2010-01-07T13:26:00","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?p=14036"},"modified":"2022-05-01T17:50:47","modified_gmt":"2022-05-01T08:50:47","slug":"20100107","status":"publish","type":"post","link":"https:\/\/www.jedat.co.jp\/en\/events-en\/20100107\/","title":{"rendered":"Jedat Exhibits at The Electronic Design and Solution Fair 2010"},"content":{"rendered":"\n
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\"\" Jedat Inc.<\/strong><\/h3>\n<\/div>\n\n\n\n
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HOME<\/a> ><\/span> <\/p>\n<\/div>\n\n\n\n

Events<\/a><\/div><\/div>\n\n\n\n
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Jedat Exhibits at The Electronic Design and Solution Fair 2010<\/span><\/h2>\n\n\n\n

2010.1.7<\/p>\n\n\n\n

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Jedat Exhibits at The Electronic Design and Solution Fair 2010, Pacifico Yokohama.<\/span><\/strong><\/p>\n\n\n\n

\u3010 Exhibition summary \u3011<\/span><\/strong><\/p>\n\n\n\n

\u25c6 The introduction of C3 (Circuit-Cube): The next generation integrated IC design tool.<\/strong><\/h4>\n\n\n\n

C3 is the next generation circuit design tool which seamlessly puts together each process of design flow: schematic entry, simulation control, waveform display and simulation result analysis. And substantially improves the design efficiency of PVT corner verification and circuit constant optimization ,in addition it can accumulate & reuse circuit information and design know-how.<\/p>\n\n\n\n

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\u25c6 The proposal regarding the substantial improvement of design efficiency and quality by the total design environment.<\/strong><\/h4>\n\n\n\n

Introduces the latest constraint driven design environment and its adoption effect, which includes integrated circuit design, high accuracy floor plan and the automatic layout design.<\/p>\n\n\n\n

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\u25c6 The introduction of the latest features of HOTSCOPE – Super high- speed display & analysis browser for Large-scale LSI data –<\/strong><\/h4>\n\n\n\n

Introduces the features which are supported with the latest version of HOTSCOPE: Automatic schematic generation from the layout, remote display function, and GDS conversion from the SEM image outline, etc.<\/p>\n\n\n\n

We are looking forward to your visit on the day.<\/p>\n\n\n\n

Name<\/td>Electronic Design and Solution Fair 2010<\/a>
(EDSFair2010)<\/td><\/tr>
Schedule<\/td>Thursday, January 28 & Friday, January 29, 2010
10:00 a.m. to 6:00 p.m<\/td><\/tr>
Location<\/td>Pacifico Yokohama<\/a> (Exhibition Hall, Annex Hall)
1-1-1, Minato Mirai, Nishi-ku, Yokohama 220-0012<\/td><\/tr>
Jointly held event<\/td>The 17th FPGA\/PLD Design Conference<\/td><\/tr>
Booth No.<\/td>313<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
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