{"id":11014,"date":"2022-03-05T23:12:34","date_gmt":"2022-03-05T14:12:34","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?page_id=11014"},"modified":"2025-11-06T13:46:42","modified_gmt":"2025-11-06T04:46:42","slug":"partner_eda","status":"publish","type":"page","link":"https:\/\/www.jedat.co.jp\/en\/partner_eda\/","title":{"rendered":"EDA Tools of the Partners"},"content":{"rendered":"\n

EDA Tools of the Partners<\/h2>\n\n\n\n
<\/div>\n\n\n\n

SOC design and manufacturing image analysis environments of companies partnered with Jedat.<\/p>\n\n\n\n\n\n\"BAUM\"\n\"ScientificAnalog\"\n\"PRIMARIUS\"\n\"BAUM\"\n\"SX-Meister\"\n\"PRIMARIUS\"\n\"SX-Meister\"\n\"PRIMARIUS\"\n\"SimYog\"\n\"HOTSCOPE\"\n\n\n\n\"PRIMARIUS\"\n\"SimplifyDA\"\n\n\"SiliconCreations\"\n\"TrueChip\"\n\n\"ANCL\"\n<\/map>\n\n\n\n

\"\"<\/figure>\n\n\n\n

<\/a><\/p>\n\n\n\n

 <\/p>\n\n\n\n

License Management<\/p><\/td>

\"\"<\/a><\/figure><\/td>

HPC environment integrated operation middleware ShareTask<\/p><\/td><\/tr>

RTL Design<\/p>

\u00a0 AI-driven RTL Design&Verification <\/p><\/td>

\"\"<\/a><\/td>Agentic AI-driven RTL Design&Verification<\/td><\/tr>

RTL Design<\/p>

  Digital Implementation and Verification 
  Analog Implementation and Verification<\/p><\/td>

\"\"<\/a><\/figure><\/td>

Generate high quality SystemVerilog models from analog circuits and verify<\/p><\/td><\/tr>

RTL Design<\/p>

  Low-power Design<\/p><\/td>

\"\"<\/a><\/figure><\/td>

RTL high accuracy and high speed power consumption analysis<\/p><\/td><\/tr>

SPICE Modeling<\/p>

Analog ,Chip-level Verification
Noise Measurement<\/p><\/td>

\"\"<\/a><\/figure><\/td>

SPICE Simulator, Modelling tool, Noise measurement<\/p><\/td><\/tr>

Analog Implementation and Verification<\/p><\/td>

\"\"<\/a><\/figure><\/td>

Integrated Circuit design and layout design system<\/p><\/td><\/tr>

IP<\/p><\/td>

\"\"<\/a><\/figure><\/td>

The most-advanced process IP: PLL\/SerDes\/LVDS-IO<\/p><\/td><\/tr>

IP<\/p><\/td>

\"\"<\/a><\/td>

The most-advanced process IP: ADC \/ DAC \/ Regulator<\/p><\/td><\/tr>

IP<\/p><\/td>

\"\"<\/a><\/figure><\/td>

Verification IP Tool set (USB~AMBA over80)<\/p><\/td><\/tr>

IP<\/p><\/td>

\"\"<\/a><\/figure><\/td>

PTU ( Protocol Termination Unit )<\/p><\/td><\/tr>

EM analysis<\/p><\/td>

\"\"<\/a><\/td>

EM analysis platform   IC\u30fbPackage\u30fbPCB<\/p><\/td><\/tr>

Mask Data Preparation (MDP)<\/p><\/td>

\"\"<\/a><\/figure><\/td>

MDP tool set<\/p><\/td><\/tr>

Cross section shape simulation<\/p><\/td>

\"\"<\/a><\/figure><\/td>

Cross section shape simulation<\/p><\/td><\/tr>

Process simulation<\/p><\/td>

\"\"<\/a><\/figure><\/td>

Plasma etching simulation<\/p><\/td><\/tr>

Board Implementation<\/p><\/td>

\"\"<\/a><\/figure><\/td>

High wiring rate topology-based auto routing<\/p><\/td><\/tr>

EMC Verification<\/p><\/td>

\"\"<\/a><\/td>

EMC Virtual Laboratory (RE\/CE\/RI\/CI)<\/p><\/td><\/tr>

Photomask Verification<\/p><\/td>

\"\"<\/a><\/figure><\/td>

Analysis browser for DFM\/Photomask verification<\/p><\/td><\/tr>

Image and defect analysis<\/p><\/td>

\u00a0\"\"<\/a><\/td>

AI-driven image and defect analysis<\/p><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

 <\/p>\n\n\n

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\"\"<\/figure>\n<\/div>","protected":false},"excerpt":{"rendered":"

EDA Tools of the Partners SOC design and manufacturing image analysis environments of companies partnered with […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":8,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","_locale":"en_US","_original_post":"https:\/\/www.jedat.co.jp\/?page_id=4958","_vk_print_noindex":"","vkExUnit_EyeCatch_disable":"","_veu_custom_css":"","veu_display_promotion_alert":"common","_exclude_from_list_pages":"","vkexunit_cta_each_option":"disable","vkExUnit_childPageIndex":"","vkExUnit_pageList_ancestor":"","vkExUnit_contact_enable":"","vk_page_header_image":5155,"vk_page_header_image_sp":5155,"header_top_description":"","footnotes":""},"categories":[193],"tags":[],"class_list":["post-11014","page","type-page","status-publish","hentry","category-partner_eda","en-US"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Jett","author_link":"https:\/\/www.jedat.co.jp\/author\/jedattraining\/"},"uagb_comment_info":0,"uagb_excerpt":"EDA Tools of the Partners SOC design and manufacturing …","lightning_design_setting_object":{"layout":"col-two","hidden_page_header":"","hidden_breadcrumb":"","siteContent_padding":"","header_trans":"","section_base":"default"},"_links":{"self":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/11014","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/comments?post=11014"}],"version-history":[{"count":8,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/11014\/revisions"}],"predecessor-version":[{"id":35002,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/11014\/revisions\/35002"}],"wp:attachment":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/media?parent=11014"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/categories?post=11014"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/tags?post=11014"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}