{"id":10570,"date":"2022-02-26T22:49:26","date_gmt":"2022-02-26T13:49:26","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?page_id=10570"},"modified":"2022-10-12T12:14:12","modified_gmt":"2022-10-12T03:14:12","slug":"application","status":"publish","type":"page","link":"https:\/\/www.jedat.co.jp\/en\/sx-meister\/application\/","title":{"rendered":"Applied Field"},"content":{"rendered":"\n

Applied Field<\/h2>\n\n\n\n

LSI Design<\/strong><\/h2>\n\n\n\n
\n

\u25a0<\/mark>Analog \/ RF<\/strong><\/h2>\n\n\n\n

Op Amp, DAC\/ADC, PLL, Filter\uff08LPF, BPF, HPF\uff1aRC, SC, Gm\uff09, Comparator, Regulator, Reset IC, Motor driver, LED light control, Clock, Clock generator, LNA\uff08Low Noise Amplifier\uff09, Power Amp, SAW, SiGeHBT, GaAsFET, MMIC, RFIC, SS clock generator<\/p>\n\n\n\n

  • Actualizes substantial shortening of the design period by the tuning function that meets circuit specification<\/li>
  • High accuracy area estimation by the high quality placement engine<\/li>
  • Achieves epoch-making automation with high density automatic Placement & Router tool for analog<\/li><\/ul>\n\n\n\n

    \u25a0<\/mark>Display Driver<\/strong><\/h2>\n\n\n\n

    LCD driver, LCD controller, Plasma driver, Imager driver, Controller, LED driver, Buffer<\/p>\n\n\n\n

    • Pursues the optimum conditions of the area and timing with the high accuracy top-level floor planne<\/li>
    • Efficient processing for layout shapes with high aspect ratio<\/li>
    • Actualizing the epoch-making automation which considers area, cost, performance with high accuracy automatic P&R tool for LCD<\/li>
    • Provides co-verification environment of LCD
      Achieves dynamic verification environment of driver IC and pursues extremity efficiency<\/li>
    • Be actualized Cell library latent defectiveness risk
      Improves spectacularly the library quality with high modification frequency<\/li><\/ul>\n\n\n\n

      \u25a0<\/mark>Power<\/strong><\/h2>\n\n\n\n

      Power IC, Power supply IC, Charge IC, SW regulator, Converter, Inverter, IGBT, Thyristor<\/p>\n\n\n\n

      • Actualizes substantial shortening of the design period by the tuning function that meets circuit specification<\/li>
      • Offers interactive EM\/IR Drop verification method which supports high voltage and high current power ICs Constraint driven integrated design environment<\/li>
      • Generates special device by the parameterized cell and reuse of design property
        Actualizes work saving and quality improvement<\/li><\/ul>\n\n\n\n

        \u25a0<\/mark>Memory<\/strong><\/h2>\n\n\n\n

        DRAM, SRAM, NAND\/NOR Flash Memory, FeRAM, MRAM, PRAM, ReRAM, Mask ROM<\/p>\n\n\n\n

        • Achieves substantial efficiency improvement with circuit design environment which supports large scale memory array<\/li>
        • Achieves automation with high density automatic P&R tool for memory layout<\/li>
        • Offers high speed layout verification tool that supports hierarchical design
          Possible to take measures to design error at the early stage<\/li>
        • Automates library development and offers substantial quality improvement with SRAM\/ROM dedicated characterization tool<\/li><\/ul>\n\n\n\n

          \u25a0<\/mark>Microcomputer<\/strong><\/h2>\n\n\n\n

          Microprocessor, DSP, Microcontroller<\/p>\n\n\n\n

          \u30fbSupports flexible layout design capability with circuit hierarchy modification function<\/p>\n\n\n\n

          \u30fbHigh accuracy area estimation by the placement engine<\/p>\n\n\n\n

          \u3000Available for early checking of the man-hour and the cost<\/p>\n\n\n\n

          \u30fbReduces design period of large scale data with high speed automatic P&R features<\/p>\n\n\n\n

          \u30fbAutomates library development and improves quality by the dedicated standard cell characterization tool<\/p>\n\n\n\n

          \u25a0<\/mark>Logic<\/strong><\/h2>\n\n\n\n

          ASCP\/USIC, ASSP, ASIC, Gate Array, Cell Base, Programmable ASIC, Embedded Array<\/p>\n\n\n\n

          • Industry top class super high speed processing of large-scale chip level data<\/li>
          • Reducing manual correction work after automatic P&R with the high speed layout editor<\/li><\/ul>\n\n\n\n

            \u25a0<\/mark>Discrete<\/strong><\/h2>\n\n\n\n

            Power MOSFET, Small Signal Transistor, Diode<\/p>\n\n\n\n

            • Actualizes substantial shortening of design period by the tuning function that meets circuit specification<\/li>
            • Offers design efficiency improvement with error free operation depending on the high-speed net driven editor<\/li>
            • Improves design efficiency and quality by providing automatic chip-level layout for IGBT\/RC-IGBT\/SiC and a post-layout simulation environment<\/li><\/ul>\n\n\n\n

              \u25a0<\/mark>Opt<\/strong><\/h2>\n\n\n\n

              CMOS Image Sensor, CCD Image Sensor, LED, Semiconductor Laser, Photodiode, Solar Cell, Phototransister, Photothyristor, Photocoupler, Photo MOSFET, Imager<\/p>\n\n\n\n

              • Pursuit of area and timing optimum conditions by the high accuracy top-level floor planner<\/li>
              • Possible to high accuracy area estimation which includes various blocks by the high quality placement engine
                Available for early checking of the man-hour and the cost<\/li>
              • Provides flexible fine processing edit technology and has flexibility in all kinds of design category<\/li>
              • Achieves epoch-making automation with high density automatic P & R tool for analog layout<\/li><\/ul>\n\n\n\n

                \u25a0<\/mark>Sensor<\/strong><\/h2>\n\n\n\n

                Acceleration sensor, Magnetic sensor, Pressure sensor, Temperature sensor, Gyro sensor, UV sensor, Sensor signal processing, Fingerprint authentication IC, RFID<\/p>\n\n\n\n

                • Operates together with mechanical CAD system<\/li><\/ul>\n\n\n\n

                  The integrated layout environment with accumulated fine processing technology<\/p>\n\n\n\n

                  • Automatic generation and of an arbitrary shape and I\/F development are possible by user programming language
                    Efficiency of complicated tasks.<\/li><\/ul>\n\n\n\n
                    <\/div>\n\n\n\n
                    \n\n\n\n
                    <\/div>\n\n\n\n

                    Flat Panel Display Design<\/strong><\/h2>\n\n\n\n
                    • FPD (Active\/Passive matrix\/a-Si\/LTPS\/HTPS\/OLED\/Electronic paper\/IGZO\/Touch panel etc.)<\/li>
                    • Color filter<\/li><\/ul>\n<\/div><\/div>\n","protected":false},"excerpt":{"rendered":"

                      Applied Field LSI Design \u25a0Analog \/ RF Op Amp, DAC\/ADC, PLL, Filter\uff08LPF, BPF, HPF\uff1aRC, SC, Gm\uff09, Comparator, Regu […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":10578,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","_locale":"en_US","_original_post":"https:\/\/www.jedat.co.jp\/?page_id=5177","vkexunit_cta_each_option":"disable","footnotes":""},"categories":[154],"tags":[],"class_list":["post-10570","page","type-page","status-publish","hentry","category-sx-meister","en-US"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Jett","author_link":"https:\/\/www.jedat.co.jp\/author\/jedattraining\/"},"uagb_comment_info":0,"uagb_excerpt":"Applied Field LSI Design \u25a0Analog \/ RF Op Amp, DAC\/ADC, …","_links":{"self":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10570","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/comments?post=10570"}],"version-history":[{"count":0,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10570\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10578"}],"wp:attachment":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/media?parent=10570"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/categories?post=10570"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/tags?post=10570"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}