{"id":10548,"date":"2022-02-26T21:36:18","date_gmt":"2022-02-26T12:36:18","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?page_id=10548"},"modified":"2022-10-12T12:03:29","modified_gmt":"2022-10-12T03:03:29","slug":"panel_layout_verification","status":"publish","type":"page","link":"https:\/\/www.jedat.co.jp\/en\/fpd_design\/panel_layout_verification\/","title":{"rendered":"Panel Layout Verification"},"content":{"rendered":"\n

Panel Layout Verification<\/h2>\n\n\n\n

Total support for FPD layout verification from pixel cell characteristic analysis to top panel DRC\/ERC\/LVS\/LPE verification<\/strong><\/strong><\/h2>\n\n\n\n
  • Full panel high-speed DRC\/ERC\/LVL verification by hierarchical processing<\/li>
  • High-speed, high-accuracy verification for the entire array<\/li><\/ul>\n\n\n\n
    \n
    <\/div>\n<\/div>\n\n\n\n
    \n
    \n
    \n
    \"\"<\/figure>\n<\/div>\n\n\n\n
    \n

    Interactive DRC\/LVS Tool<\/strong><\/strong><\/span> <\/span> <\/p>\n\n\n\n

    SX-Meister<\/small> iDRC \/ iLVS<\/span><\/strong> <\/strong><\/em><\/h2>\n\n\n\n

    <\/p>\n<\/div>\n<\/div>\n\n\n\n

    \u25a0<\/mark>Reduce sign-off verification time<\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
    \n
    \n
    • Debug environment that allows easy layout modification<\/li>
    • Real-time DRC linked with layout input\/editing<\/li>
    • High-precision DRC compatible with any-angle figures<\/li>
    • Acceleration of array verification by hierarchical processing<\/li>
    • LVS that supports special LCD device recognition<\/li>
    • Design rules can be easily created and edited using the GUI<\/li>
    • Rule import of third-party verification tool<\/li><\/ul>\n<\/div>\n<\/div>\n\n\n
      \n
      \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n
      \n
      \n
      \n
      \"\"<\/figure>\n<\/div>\n\n\n\n
      \n

      LVL Tool for FPD<\/strong><\/strong><\/strong><\/span> <\/p>\n\n\n\n

      SX-Meister<\/small> FineLVL<\/span><\/strong> <\/strong><\/em><\/h2>\n\n\n\n

      <\/p>\n<\/div>\n<\/div>\n\n\n\n

      \u25a0<\/mark>Supports comparative verification of layout patterns<\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
      \n
      \n
      • Pattern comparison of a specific layer<\/li>
      • Pattern comparison between hierarchical cells<\/li>
      • Hierarchical consistency comparison<\/li>
      • Simple rule definition<\/li>
      • Supports flat processing of layers<\/li><\/ul>\n<\/div>\n<\/div>\n\n\n
        \n
        \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n
        \n
        \n
        \n
        \"\"<\/figure>\n<\/div>\n\n\n\n
        \n

        ERC Tool for FPD<\/strong><\/strong><\/strong><\/strong><\/span> <\/p>\n\n\n\n

        SX-Meister<\/small> FineERC<\/span><\/strong> <\/strong><\/em><\/h2>\n<\/div>\n<\/div>\n\n\n\n

        \u25a0<\/mark>Supports wiring open and short check<\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
        \n
        \n
        • Equipotential tracking and verification of polygon figures<\/li>
        • High-speed verification of pixel array by hierarchical processing<\/li>
        • Short path search<\/li>
        • Simple rule definition<\/li><\/ul>\n<\/div>\n<\/div>\n\n\n
          \n
          \"\"<\/figure>\n<\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"

          Panel Layout Verification Total support for FPD layout verification from pixel cell characteristic analysis to […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":10517,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","_locale":"en_US","_original_post":"https:\/\/www.jedat.co.jp\/?page_id=5109","vkexunit_cta_each_option":"disable","footnotes":""},"categories":[191],"tags":[93,94,95],"class_list":["post-10548","page","type-page","status-publish","hentry","category-fine_pattern","tag-fineerc","tag-finelvl","tag-idrc-ilvs","en-US"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Jett","author_link":"https:\/\/www.jedat.co.jp\/author\/jedattraining\/"},"uagb_comment_info":0,"uagb_excerpt":"Panel Layout Verification Total support for FPD layout …","_links":{"self":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10548","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/comments?post=10548"}],"version-history":[{"count":0,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10548\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10517"}],"wp:attachment":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/media?parent=10548"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/categories?post=10548"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/tags?post=10548"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}