{"id":10525,"date":"2022-02-26T20:50:51","date_gmt":"2022-02-26T11:50:51","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?page_id=10525"},"modified":"2022-10-12T12:02:24","modified_gmt":"2022-10-12T03:02:24","slug":"panel_layout_design","status":"publish","type":"page","link":"https:\/\/www.jedat.co.jp\/en\/fpd_design\/panel_layout_design\/","title":{"rendered":"Panel Layout Design"},"content":{"rendered":"\n

Panel Layout Design<\/h2>\n\n\n\n

Significantly Reduce Design TAT with Dedicated Functions Specialized for FPD Design<\/strong><\/strong><\/h2>\n\n\n\n
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\u25cf High-performance layout editor that realizes error-free design and shortens design period<\/p>\n\n\n\n

  • Rule-driven and net-driven design to reduce design mistakes<\/li>
  • Net information can be added to existing polygon data to make it net driven.<\/li>
  • Push Aside function that retains design rules between polygon figures<\/li><\/ul>\n\n\n\n

    \u25cf Significantly reduce design TAT with dedicated functions specialized for FPD design<\/p>\n\n\n\n

    • The wiring input time is shortened by the wiring function that keeps the wiring resistance value constant, the bundling function, and the trim function.<\/li><\/ul>\n\n\n\n
      • Shorten verification time with various verification tools dedicated to FPD design<\/li><\/ul>\n\n\n\n

        \u25cf Possible to enter a wealth of document information<\/p>\n\n\n\n

        • Dimension input, drawing frame input<\/li>
        • Enter Japanese comments<\/li><\/ul>\n<\/div>\n<\/div>\n\n\n\n
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          \"\"<\/figure>\n<\/div>\n\n\n\n
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          Layout Design System<\/strong><\/strong><\/strong> <\/span> <\/span><\/span> <\/span> <\/p>\n\n\n\n

          SX-Meister<\/small> Ismo-Advanced<\/span><\/strong> <\/strong><\/em><\/h2>\n<\/div>\n<\/div>\n\n\n\n

          \u25a0<\/mark>Standard of FPD layout tool<\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
          • Fusion with abundant automated design tools and verification tools<\/li>
          • Supports various design styles (polygon-based, rule-driven, net-driven)<\/li>
          • Large-scale support, high-speed data processing<\/li>
          • Powerful wiring editing function as standard equipment
            PushAside, bus wiring function, automatic VIA transfer, wiring guidance, etc.<\/li>
          • User-specific device generation using parameterized cells<\/li>
          • Intuitive, excellent operability and easy customization<\/li>
          • Abundant input and output
            DXF, Gerber, GDSII, OASIS
            EDIF Schematic, Spice Netlist, Verilog-HDL
            Other tools’ rule information<\/li><\/ul>\n\n\n
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            \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n
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            \"\"<\/figure>\n<\/div>\n\n\n\n
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            Layout Editor for FPD and Fine Pattern Design<\/strong><\/strong><\/span> <\/span> <\/p>\n\n\n\n

            SX-Meister<\/small> FineArts<\/span><\/strong> <\/strong><\/em><\/h2>\n\n\n\n

            <\/p>\n<\/div>\n<\/div>\n\n\n\n

            \u25a0<\/mark>Supports FPD design and fine pattern design<\/strong><\/strong>
            \u3000Supports mechanical CAD functions required for mask design<\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
            • Abundant pattern input editing functions
              Arrangement of special shape patterns (elliptical arc shape, cam shape, swirl, 7-segment, etc.)
              Auxiliary line input
              Automatic wiring that keeps the resistance value constant
              Wiring resistance adjustment
              Conversion from zero-width line to boundary figure
              Bundle line connection within a specified area<\/li>
            • Various report output (resistance calculation, area calculation, etc.)<\/li>
            • Drawing frame layout, input and edit of dimension lines<\/li><\/ul>\n\n\n
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              \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n
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              \"\"<\/figure>\n<\/div>\n\n\n\n
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              Placement and Routing Tool for Free-form Panels<\/strong><\/span><\/strong><\/strong><\/strong> <\/span><\/span> <\/span> <\/p>\n\n\n\n

              SX-Meister<\/small> FineFFP<\/span><\/strong> <\/strong><\/em><\/h2>\n<\/div>\n<\/div>\n\n\n\n

              \u25a0<\/mark>Dramatically improve design efficiency with automatic functions specialized for free-form panel design<\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
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              • Automatic wiring between the pixel and the driver
                Data \/ Gate automatic wiring
                GOA cell automatic placement<\/li>
              • Automatic mask generation of aperture
                Automatic mask generation of the aperture on the panel border line
                Automatic mask generation using CSV file<\/li><\/ul>\n\n\n
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                \"\"<\/figure>\n<\/div><\/div>\n\n\n\n
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                \"\"<\/figure>\n<\/div><\/div>\n<\/div>\n<\/div><\/div>\n\n\n\n
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                \"\"<\/figure>\n<\/div>\n\n\n\n
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                FPC Wiring Tool<\/strong><\/span><\/strong><\/strong><\/strong> <\/span> <\/p>\n\n\n\n

                SX-Meister<\/small> FineFPC<\/span><\/strong> <\/strong><\/em><\/h2>\n\n\n\n

                <\/p>\n<\/div>\n<\/div>\n\n\n\n

                \u25a0<\/mark>Batch automatic wiring considering wiring conditions between IC and FPC<\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
                • Automatic generation using CSV file
                  IC \/ FPC cell
                  Special connection information (m vs. n)<\/li>
                • Automatic determination of wiring width, Verification of wiring results by resistance value
                  Resistance value calculation linked with FPD resistance calculation tool (FineAcres)<\/li><\/ul>\n\n\n
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                  \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n
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                  \"\"<\/figure>\n<\/div>\n\n\n\n
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                  Drawing Creation Tool<\/strong><\/strong><\/strong><\/span> <\/span><\/span> <\/span> <\/p>\n\n\n\n

                  SX-Meister<\/small> FineSketch<\/span><\/strong> <\/strong><\/em><\/h2>\n<\/div>\n<\/div>\n\n\n\n

                  \u25a0<\/mark>Supports drawing data creation based on design data<\/strong><\/strong><\/strong><\/strong><\/strong><\/strong><\/h2>\n\n\n\n
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                  • Create drawing data from design data
                    Enlarged view, annotation view\u3000\u3000
                    Mask configuration diagram, cross-sectional structure diagram<\/li>
                  • Unified management of design data and drawing data
                    Automatically generate new drawings based on design changes
                    Comparison (LVL) and display of old and new drawings\u3000
                    Drawing revision control<\/li><\/ul>\n<\/div>\n\n\n\n
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                    \"\"<\/figure>\n<\/div><\/div>\n<\/div>\n\n\n
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                    \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n

                    <\/p>\n","protected":false},"excerpt":{"rendered":"

                    Panel Layout Design Significantly Reduce Design TAT with Dedicated Functions Specialized for FPD Design \u25cf High […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":10517,"menu_order":2,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","_locale":"en_US","_original_post":"https:\/\/www.jedat.co.jp\/?page_id=5118","_vk_print_noindex":"","vkExUnit_EyeCatch_disable":"","_veu_custom_css":"","veu_display_promotion_alert":"","_exclude_from_list_pages":"","vkexunit_cta_each_option":"disable","vkExUnit_childPageIndex":"","vkExUnit_pageList_ancestor":"","vkExUnit_contact_enable":"","vk_page_header_image":492,"vk_page_header_image_sp":492,"header_top_description":"","footnotes":""},"categories":[190],"tags":[38,37,88,89,63],"class_list":["post-10525","page","type-page","status-publish","hentry","category-fpd_design","tag-finearts","tag-fineffp","tag-finefpc","tag-finesketch","tag-ismo-advanced","en-US"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Jett","author_link":"https:\/\/www.jedat.co.jp\/author\/jedattraining\/"},"uagb_comment_info":0,"uagb_excerpt":"Panel Layout Design Significantly Reduce Design TAT wit…","lightning_design_setting_object":{"layout":"col-two","hidden_page_header":"","hidden_breadcrumb":"","siteContent_padding":"","header_trans":"","section_base":"default"},"_links":{"self":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10525","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/comments?post=10525"}],"version-history":[{"count":0,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10525\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10517"}],"wp:attachment":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/media?parent=10525"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/categories?post=10525"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/tags?post=10525"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}