{"id":10521,"date":"2022-02-25T23:42:03","date_gmt":"2022-02-25T14:42:03","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?page_id=10521"},"modified":"2024-07-01T15:38:51","modified_gmt":"2024-07-01T06:38:51","slug":"fpd_circuit_design","status":"publish","type":"page","link":"https:\/\/www.jedat.co.jp\/en\/fpd_design\/fpd_circuit_design\/","title":{"rendered":"Circuit Design"},"content":{"rendered":"\n

Circuit Design<\/h2>\n\n\n\n
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Circuit design environment for each design application, from simulation to layout design and LVS verification<\/strong><\/strong><\/h2>\n\n\n\n
    \n
  • Design and verification environment that integrates circuit entry, simulation execution control, and waveform measurement<\/li>\n\n\n\n
  • Array structure definition corresponding to the FPD circuit configuration<\/li>\n\n\n\n
  • Parasitic definition of parasitic wiring effect model and back annotation I\/F<\/li>\n\n\n\n
  • User I\/F that supports shortcuts and handwritten command input<\/li>\n<\/ul>\n<\/div>\n<\/div>\n\n\n\n
    \n
    \n
    \n
    \"SX-Meister\"<\/figure>\n<\/div>\n\n\n\n
    \n

    Integrated Circuit Design System<\/strong><\/strong><\/span> <\/strong><\/span> <\/span> <\/span><\/span> <\/span> <\/p>\n\n\n\n

    SX-Meister<\/small> Asca-Advanced <\/strong> <\/strong> <\/strong> <\/strong> <\/strong> <\/strong> <\/strong><\/em><\/h2>\n<\/div>\n<\/div>\n\n\n\n

    \u25a0<\/mark>Circuit design platform that integrates essential functions for circuit design<\/strong><\/strong><\/h2>\n\n\n\n
      \n
    • A seamless circuit design platform is realized by integrating schematic entry, simulation execution control, and waveform analysis viewer.<\/li>\n<\/ul>\n\n\n
      \n
      \"\"<\/figure>\n<\/div>\n\n\n

      \u25a0<\/mark>Efficiency of circuit analysis and verification work, which involves many repetitive tasks<\/strong><\/strong><\/h2>\n\n\n\n
        \n
      • Easy simulation control by GUI<\/li>\n\n\n\n
      • Automatic feedback of analysis results to the schematic<\/li>\n\n\n\n
      • Stress-free waveform measurement and analysis by high-speed display of large-scale waveform data<\/li>\n<\/ul>\n\n\n\n

        \u25a0<\/mark>Schematic editor for high-speed handling of large-scale FPD schematics<\/strong><\/strong><\/h2>\n\n\n\n
          \n
        • Large model pixel array circuit design support
          Parametric 2D array editing function
          Trade-off analysis by parametric modeling of wiring parasitic effect
          Back annotation of layout wiring parasitic information<\/li>\n\n\n\n
        • High-speed editing of large-scale circuits, ultra-high-speed netlist output<\/li>\n\n\n\n
        • Abundant input \/ output
          EDIF Schematic, Spice Netlist, Verilog-HDL<\/li>\n\n\n\n
        • Excellent user-friendly operability
          Shortcut key
          Handwriting command
          Unified GUI<\/li>\n\n\n\n
        • Easy customization function
          GUI and command customization by AXEL language
          Customizing the netlist output format with a format file
          Automatic calculation of design element parameters by AXEL callback function<\/li>\n<\/ul>\n\n\n\n
          \n
          \n
          \"\"<\/figure>\n<\/div><\/div>\n\n\n\n
          \n
          \"\"<\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n

          <\/p>\n<\/div><\/div>\n\n\n\n

          \n
          \n
          \n
          \"SX-Meister\"<\/figure>\n<\/div>\n\n\n\n
          \n

          <\/span><\/span><\/span><\/span>Simulation Waveform Analysis<\/strong><\/strong><\/span> <\/span> <\/span><\/span><\/span> <\/span> <\/span> <\/p>\n\n\n\n

          SX-Meister<\/small> <\/em><\/small><\/strong>SpiceChart<\/span><\/strong><\/em><\/small> <\/strong><\/span> <\/strong> <\/strong> <\/strong> <\/strong> <\/strong> <\/strong><\/em><\/h2>\n<\/div>\n<\/div>\n\n\n\n

          \u25a0<\/span>Intuitive operation enables stress-free analysis<\/b><\/strong><\/strong><\/h2>\n\n\n\n
          \n
          \n
            \n
          • Post-layout simulation-scale waveform display at ultra-high speed
            Display 5GB order in 1 minute<\/li>\n\n\n\n
          • Command execution with just Drag & Drop and click operation<\/li>\n\n\n\n
          • Document creation support
            Enter Japanese comments, copy and paste measured values<\/li>\n\n\n\n
          • Abundant measurement functions
            Simultaneous display of multiple analyzes by multi-tab<\/li>\n\n\n\n
          • Jitter analysis, histogram display<\/li>\n\n\n\n
          • EyeDiagram, AD \/ DA conversion<\/li>\n\n\n\n
          • Easy-to-read display
            Measurement result display by XY cursor and point cursor<\/li>\n\n\n\n
          • Measurement value color and background color can be customized<\/li>\n\n\n\n
          • Supports various format
            str0 \/ ac0 \/ dc0, fsdb, raw, psf, csv<\/li>\n<\/ul>\n<\/div>\n<\/div>\n\n\n
            \n
            \"\"<\/figure>\n<\/div><\/div><\/div>\n\n\n\n

            <\/p>\n","protected":false},"excerpt":{"rendered":"

            Circuit Design Circuit design environment for each design application, from simulation to layout design and LV […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":10517,"menu_order":1,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","_locale":"en_US","_original_post":"https:\/\/www.jedat.co.jp\/?page_id=5085","_vk_print_noindex":"","vkExUnit_EyeCatch_disable":"","_veu_custom_css":"","veu_display_promotion_alert":"common","_exclude_from_list_pages":"","vkexunit_cta_each_option":"disable","vkExUnit_childPageIndex":"","vkExUnit_pageList_ancestor":"","vkExUnit_contact_enable":"","vk_page_header_image":396,"vk_page_header_image_sp":396,"header_top_description":"","footnotes":""},"categories":[190],"tags":[66,80,81],"class_list":["post-10521","page","type-page","status-publish","hentry","category-fpd_design","tag-asca-advanced","tag-msim-lcd","tag-spicechart","en-US"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Jett","author_link":"https:\/\/www.jedat.co.jp\/author\/jedattraining\/"},"uagb_comment_info":0,"uagb_excerpt":"Circuit Design Circuit design environment for each desi…","lightning_design_setting_object":{"layout":"col-two","hidden_page_header":"","hidden_breadcrumb":"","siteContent_padding":"","header_trans":"","section_base":"default"},"_links":{"self":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10521","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/comments?post=10521"}],"version-history":[{"count":1,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10521\/revisions"}],"predecessor-version":[{"id":25469,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10521\/revisions\/25469"}],"up":[{"embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/pages\/10517"}],"wp:attachment":[{"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/media?parent=10521"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/categories?post=10521"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.jedat.co.jp\/wp-json\/wp\/v2\/tags?post=10521"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}