The custom layout design platform that realizes both high quality and shortening design time by reusing the craftsmanship and automating layout design that coordinates designers and automatic tools.<\/strong><\/p>\n\n\n\n
\u25a0<\/mark>Features<\/strong><\/h2>\n\n\n\n
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Uses a variety of design techniques, to achieve a degree of freedom and \u3000scalable design environment.<\/li>\n\n\n\n
Support large scale data (Stream 100 GB scale, 10 million net scale)<\/li>\n\n\n\n
Cooperates with polygon editing and net driven editing – Enable rule-driven editing with automatic electrical potential recognition \u3000and net tracking funct<\/li>\n\n\n\n
Template based constraint driven layout – Improve design quality using templates such as Pair group layout \u3000\u3000<\/li>\n\n\n\n
generation<\/li>\n\n\n\n
Shorten the design period with a variety of optional tools specialized for a \u3000design target<\/li>\n\n\n\n
Analysis and learning function – Follow the work procedure of the designer with craftsmanship, shorten\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 the design period with the optimum procedure<\/li>\n<\/ul>\n\n\n
Realizes a highly flexible and scalable design environment with a wide variety of design methods Support for large scale data (Stream 100 Gbyte scale, 10 million net scale or more) Shorten TAT by using a wide range of optional tools specialized for the design target<\/strong><\/strong><\/p>\n\n\n\n
Integration of polygon editing and net-driven editing<\/strong><\/p>\n\n\n\n
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Automatic potential recognition of polygon shapes and net tracking enablerule driven editing.<\/li>\n\n\n\n
Push Aside function for wiring and automatic loop elimination function<\/li>\n\n\n\n
Automatic net construction function when wiring is input<\/li>\n<\/ul>\n\n\n\n
Constraint-driven editing<\/strong><\/p>\n\n\n\n
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Layout editing function that preserves circuit constraints<\/li>\n<\/ul>\n\n\n\n
High operability<\/strong><\/p>\n\n\n\n
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Multi-language menu (Japanese mode, English mode)<\/li>\n\n\n\n
Windows-like operability<\/li>\n<\/ul>\n\n\n
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Automatic Power Device Layout Generator<\/strong><\/strong><\/strong><\/strong> <\/p>\n\n\n\n
Automatic chip layout generation for power devices (IGBT\/RC-IGBT\/SiC).<\/strong><\/strong> Reduces design man-hours by automatically generating power device layouts from simple floorplan information without requiring complex rules and settings.<\/strong><\/p>\n\n\n\n
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Automatic generation of layout (placement and wiring) from design specifications and templates described by CSV.<\/li>\n\n\n\n
Calculate device size from chip size and template, and place main cells in array.<\/li>\n\n\n\n
Automatic cell placement on chip periphery area.<\/li>\n\n\n\n
Automatic cell placement dedicated to the main cell boundary.<\/li>\n\n\n\n
Supports modification and reallocation of main cell placement area after layout generation.<\/li>\n<\/ul>\n\n\n
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<\/figure>\n<\/div><\/div><\/div>\n\n\n\n\n\n\n![\"\"](\"https:\/\/www.jedat.co.jp\/wp-content\/uploads\/2022\/03\/semi_layout_design_powergenerator-eng.png\")
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