{"id":10457,"date":"2022-02-25T21:47:17","date_gmt":"2022-02-25T12:47:17","guid":{"rendered":"https:\/\/www.jedat.co.jp\/?page_id=10457"},"modified":"2022-11-01T14:48:25","modified_gmt":"2022-11-01T05:48:25","slug":"thesis","status":"publish","type":"page","link":"https:\/\/www.jedat.co.jp\/en\/company\/thesis\/","title":{"rendered":"Papers delivered"},"content":{"rendered":"\n

Papers delivered<\/h2>\n\n\n\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Date<\/th>\nTitle\u00a0<\/th>\nEditor\u3000<\/th>\nSchool<\/th>\nPlace<\/th>\n<\/tr>\n
26-28
Oct-22<\/th>\n		CMOS Reference Voltage Source Using Drain Current Temperature Characteristics<\/th>\nakafumi Kamio,
Tianrui Feng,
Lei Sha,
Jun-ichi Matsuda,
Takashi Hosono,
Souma Yamamoto,
Shogo Katayama,
Anna Kuwana,
Haruo Kobayashi
: Gunma University
Kouji Hirai,
Akira Suzuki,
Satoshi Yamada,
Tomoyuki Kato,
Ritsuko Kitakoga,
Takeshi Shimamura,
Gopal Adhikari,
Nobuto Ono,
Kazuhiro Miura,
Shigeya Yamaguchi
: Jedat Inc.<\/th>\n		The Seventh International Conference On Consumer Electronics (ICCE) Asia\u00a0(ICCE-Asia)<\/th>\nSouth Korea<\/th>\n<\/tr>\n
7-Mar-22<\/th>\n\u30a2\u30ca\u30ed\u30b0\u96c6\u7a4d\u56de\u8def\u9762\u7a4d\u524a\u6e1b\u306e\u305f\u3081\u306e\u30dc\u30c8\u30eb\u30cd\u30c3\u30af\u30c1\u30e3\u30cd\u30eb\u914d\u7dda\u306e\u63d0\u6848<\/th>\n\u8c37\u53e3\u548c\u5f25,
\u7530\u6e6f\u667a,
\u9ad8\u6a4b\u7be4\u53f8
\uff08\u6771\u5de5\u5927\uff09
\u8f5f\u7950\u5409,
\u5357\u8aa0
\uff08\u30b8\u30fc\u30c0\u30c3\u30c8\uff09<\/th>\n		\u96fb\u5b50\u60c5\u5831\u901a\u4fe1\u5b66\u4f1aVLSI\u8a2d\u8a08\u6280\u8853\u7814\u7a76\u4f1a<\/th>\nJapan<\/th>\n<\/tr>\n
18-Feb-21<\/th>\n\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u3092\u7528\u3044\u305f\u30c8\u30ec\u30f3\u30c1\u578bIGBT\u306e\u7d20\u5b50\u69cb\u9020\u63a8\u5b9a<\/th>\n\u6709\u99ac\u5927\u751f,
\u5b97\u5f62\u6052\u592b,
\u9ed2\u5ddd\u6566,
\u4eca\u4e95\u96c5,
\u91d1\u672c\u4fca\u5e7e<\/th>\n		\u4ee4\u548c2\u5e74\u5ea6 \u60c5\u5831\u51e6\u7406\u5b66\u4f1a\u6771\u5317\u652f\u90e8\u7814\u7a76\u4f1a<\/th>\nHirosaki, Japan<\/th>\n<\/tr>\n
7-Nov-20<\/th>\nFeedback Operation Analysis of Temperature Insensitive MOS Reference Current Source with Self Bias Circuit<\/th>\nSouma Yamamoto,
K. I.Ebisawa,
Y. Abe,
T. Ida,
Y. Shibasaki,
N.Tsukiji,
A.Kuwana,
H. Kobayashi
: Gunma University
A.Suzuki,
Y. Todoroki,
T. Kakinoki,
N. Ono,
K. Miura
: Jedat Inc.<\/th>\n		6th Taiwan and Japan Conference on Circuits and Systems
(TJCAS 2020)<\/th>\n		On-line<\/th>\n<\/tr>\n
23-Oct-20<\/th>\nOperation and Stability Analysis of Temperature Insensitive MOS Reference Current Source with Self Bias Circuit<\/th>\nSouma Yamamoto,
K. I.Ebisawa,
Y. Abe,
T. Ida,
Y. Shibasaki,
N.Tsukiji
A.Kuwana,
H. Kobayashi
: Gunma University
A.Suzuki,
Y. Todoroki,
T. Kakinoki,
N. Ono,
K. Miura
: Jedat Inc.<\/th>\n		17th International SoC Design Conference
(ISOCC 2020)<\/th>\n		Yeosu, Korea<\/th>\n<\/tr>\n
20-Feb-20<\/th>\n\u30d1\u30ef\u30fc\u30e2\u30b8\u30e5\u30fc\u30eb\u306e\u71b1\u5fdc\u529b\u9023\u6210\u89e3\u6790\u306b\u5411\u3051\u305fIGBT\u7b49\u4fa1\u56de\u8def\u30e2\u30c7\u30eb\u306b\u95a2\u3059\u308b\u691c\u8a0e<\/th>\n\u4f0a\u85e4\u98af\u592a\u3001
\u5b97\u5f62\u6052\u592b\u3001
\u9ed2\u5ddd\u6566\u3001
\u4eca\u4e95\u96c5\u3001
\u91d1\u672c\u4fca\u5e7e<\/th>\n		\u4ee4\u548c\u5143\u5e74\u5ea6\u3000\u7b2c6\u56de\u60c5\u5831\u51e6\u7406\u5b66\u4f1a\u6771\u5317\u652f\u90e8\u7814\u7a76\u4f1a<\/th>\nHirosaki, Japan<\/th>\n<\/tr>\n
5-Jun-19<\/th>\nPractical cell based analog design methodology\u2161 (AnaCell)<\/th>\nAkira Suzuki,
Yukichi Todoroki,
Tomoyuki Kato,
Masanori Kusano,
Nobuto Ono,
Kazuhiro Miura,
Kazuyuki Kawauchi
: Jedat Inc.
Takashi Ida,
Yudai Abe,
Yukiko Shibasaki,
Anna Kuwana,
Haruo Kobayashi
: Division of Electronics and Informatics, Gunma University<\/th>\n		Design Automation Conference 2019 Designer Track<\/th>\nLas Vegas, USA<\/th>\n<\/tr>\n
8-Nov-18<\/th>\nVariability in Thermo-mechanical Stress Applied to the Bonding Junction of Power MOSFET<\/th>\nToshiki Kanamoto,
Kazuaki Nomiya,
Koki Kasai,
Atsushi Kurokawa,
Masashi Imai,
Tsuneo Munakata<\/th>\n		11th ACM\/IEEE Workshop on Variability Modeling and Characterization (VMC)<\/th>\nSan Diego, USA<\/th>\n<\/tr>\n
27-Jun-18<\/th>\nPractical cell based analog design methodology (AnaCell)<\/th>\nAkira Suzuki,
Yukichi Todoroki,
Atsushi Wada,
Tomoyuki Kato,
Masanori Kusano,
NobutoOno,
Kazuhiro Miura<\/th>\n		Design Automation Conference 2018
Designer Track<\/th>\n		San Francisco, USA<\/th>\n<\/tr>\n
25-Aug-17<\/th>\nPowerMOS\u30c7\u30d0\u30a4\u30b9\u71b1\u8a2d\u8a08\u306e\u305f\u3081\u306e\u30dc\u30f3\u30c7\u30a3\u30f3\u30b0\u30ef\u30a4\u30e4\u30e2\u30c7\u30eb\u306e\u69cb\u7bc9<\/th>\n\u592a\u7530\u3000\u62d3\u78e8\uff0c
\u845b\u897f\u3000\u5b5d\u5df1\uff0c
\u4eca\u4e95\u3000\u96c5\uff0c
\u9ed2\u5ddd\u3000\u6566\uff0c
\u91d1\u672c\u3000\u4fca\u5e7e\uff0c
\u5b97\u5f62\u3000\u6052\u592b<\/th>\n		\u5e73\u621029\u5e74\u5ea6\u3000\u96fb\u6c17\u95a2\u4fc2\u5b66\u4f1a
\u6771\u5317\u652f\u90e8\u9023\u5408\u5927\u4f1a<\/th>\n		Hirosaki, Japan<\/th>\n<\/tr>\n
19-Jun-17<\/th>\nResistance Driven Routing Methodology of Power Supply Network for Low Power and Multiple Voltage Design<\/th>\nMakoto Minami,
Mathieu Molongo,
Kenji Aoyama,
Chen Lingfeng,
Zhu Xiaoke,
Kouji Ishihara,
Nobuto, Ono (Speaker),
Syunichi Kuwata,
Kazuhiro Miura,
Koutaro Hachiya<\/th>\n		Design Automation Conference 2017\u3000Designer Track<\/th>\nAustin, USA<\/th>\n<\/tr>\n
6-Jun-16<\/th>\nPLL design using automatic analog migration tool<\/th>\nAkira Suzuki,
Nobuto Ono,
Yoshiyuki Kato,
Hiroyuki Rokugawa,
Tomoyuki Kato,
Yukichi Todoroki,
Kazuhiro Miura<\/th>\n		Design Automation Conference 2016\u3000Designer Track<\/th>\nAustin, USA<\/th>\n<\/tr>\n
10-Sep-15<\/th>\n\u30a2\u30ec\u30a4\u72b6\u30b0\u30eb\u30fc\u30d7\u306e\u30b0\u30eb\u30fc\u30d7\u5185\u30d5\u30ed\u30a2\u30d7\u30e9\u30f3\u5019\u88dc\u306e\u9078\u629e\u65b9\u6cd5<\/th>\n\u5927\u4e95\u3000\u60a0\u8f14,
\u5357\u3000\u8aa0,
\u30de\u30a4\u3000\u30f4\u30a1\u30f3\u3000\u30ad\u30e5\u30fc<\/th>\n		2015\u5e74\u96fb\u5b50\u60c5\u5831\u901a\u4fe1\u5b66\u4f1a
\u30bd\u30b5\u30a4\u30a8\u30c6\u30a3\u5927\u4f1a<\/th>\n		Sendai, Japan<\/th>\n<\/tr>\n
4-Jun-15<\/th>\nCircuit Design Method for MOS Analog-Design Reuse<\/th>\n\u9234\u6728\u3000\u5f70,
\u8f5f\u3000\u7950\u5409,
\u5c0f\u91ce\u3000\u4fe1\u4efb,
\u4e09\u6d66\u3000\u4e00\u5e83<\/th>\n		Design Automation Conference 2015
Designer Track<\/th>\n		San Francisco, USA<\/th>\n<\/tr>\n
31-Jul-12<\/th>\n\u30d5\u30ea\u30c3\u30d7\u30d5\u30ed\u30c3\u30d7\u306eNBTI\u4fe1\u983c\u6027\u6027\u80fd\u89e3\u6790<\/th>\n\u6e21\u908a\u3000\u771e\u4e4b,
\u661f\u3000\u8aa0,
\u5bae\u5d0e\u3000\u6d69,
\u5c0f\u91ce\u3000\u4fe1\u4efb,
\u8702\u5c4b\u3000\u5b5d\u592a\u90ce,
\u9ed2\u5ddd\u3000\u6566<\/th>\n		\u96fb\u5b50\u60c5\u5831\u901a\u4fe1\u5b66\u4f1a
\u7b2c25\u56de \u56de\u8def\u3068\u30b7\u30b9\u30c6\u30e0\u30ef\u30fc\u30af\u30b7\u30e7\u30c3\u30d7<\/th>\n		Awaji, Japan<\/th>\n<\/tr>\n
8-Mar-12<\/th>\nPrecise Expression of nm CMOS Variability with Variance\/Covariance Statistics on Ids(Vgs)<\/th>\nKoutaro Hachiya,
Hiroo Masuda,
Okamoto Atsushi,
Masatoshi Abe,
Takeshi Mizoguchi,
Goichi Yokomizo<\/th>\n		SASIMI 2012
Technical Program Committee<\/th>\n		Beppu, Japan<\/th>\n<\/tr>\n
1-Sep-11<\/th>\nCMOS\u30c9\u30e9\u30a4\u30d0\u56de\u8def\u9045\u5ef6\u306eNBTI\u52a3\u5316\u3070\u3089\u3064\u304d\u7279\u6027\u89e3\u6790<\/th>\n\u4f50\u65b9\u3000\u525b,
\u6210\u6728\u3000\u4fdd\u6587,
\u5965\u6751\u3000\u9686\u660c,
\u91d1\u672c\u3000\u4fca\u5e7e,
\u5897\u7530\u3000\u5f18\u751f,
\u4f50\u85e4\u3000\u9ad8\u53f2,
\u6a4b\u672c\u3000\u660c\u5b9c,
\u53e4\u5ddd\u3000\u4e14\u6d0b,
\u7530\u4e2d\u3000\u6b63\u548c,
\u5c71\u4e2d\u3000\u4fca\u8f1d<\/th>\n		\u60c5\u5831\u51e6\u7406\u5b66\u4f1a
\u7814\u7a76\u90e8\u9580\u3000\u30b7\u30f3\u30dd\u30b8\u30a6\u30e0<\/th>\n		Toyohashi, Japan<\/th>\n<\/tr>\n
5-Jun-11<\/th>\nQuality Assurance Methodology of Compact MOSFET Models including Variability Effects<\/th>\nHiroo Masuda,
koutaro Hachiya,
Goichi Yokomizo<\/th>\n		Design Automation Conference 2011
User Track<\/th>\n		San Diego, USA<\/th>\n<\/tr>\n
2-Jul-10<\/th>\nRTN\u3092\u8003\u616e\u3057\u305f\u56de\u8def\u7279\u6027\u3070\u3089\u3064\u304d\u89e3\u6790\u65b9\u6cd5\u306e\u691c\u8a0e<\/th>\n\u5897\u7530\u3000\u5f18\u751f,
\u4f50\u65b9\u3000\u525b,
\u4f50\u85e4\u3000\u9ad8\u53f2,
\u6a4b\u672c\u3000\u660c\u5b9c,
\u53e4\u5ddd\u3000\u4e14\u6d0b,
\u7530\u4e2d\u3000\u6b63\u548c,
\u5c71\u4e2d\u3000\u4fca\u8f1d,
\u91d1\u672c\u3000\u4fca\u5e7e<\/th>\n		\u60c5\u5831\u51e6\u7406\u5b66\u4f1a
\u7814\u7a76\u90e8\u9580\u3000\u30b7\u30f3\u30dd\u30b8\u30a6\u30e0<\/th>\n		Toyohashi, Japan<\/th>\n<\/tr>\n
27-Aug-09<\/th>\nSRAM\u3000\u30bb\u30eb\u6b69\u7559\u307e\u308a\u89e3\u6790\u6642\u9593\u77ed\u7e2e\u306b\u5411\u3051\u305f\u30e2\u30f3\u30c6\u30ab\u30eb\u30ed\u9ad8\u901f\u5316\u624b\u6cd5\u306e\u63d0\u6848<\/th>\n\u4f50\u85e4\u3000\u4fee\u5e73,
\u8702\u5c4b\u3000\u5b5d\u592a\u90ce,
\u897f\u7530\u3000\u5f70\u7537,
\u84b2\u539f\u3000\u53f2\u6717<\/th>\n		\u60c5\u5831\u51e6\u7406\u5b66\u4f1a
\u30b7\u30b9\u30c6\u30e0LSI\u8a2d\u8a08\u6280\u8853\u7814\u7a76\u4f1a<\/th>\n		Tokyo,
Japan<\/th>\n<\/tr>\n
21-Apr-09<\/th>\nAn Automatic Design Method for MOS Analog Circuits using Reduction of Independent Design Variables Based on Topological Constraints<\/th>\nKatsuhiro Furukawa,
Yasuaki Inoue,
Saburo Hojyo<\/th>\n		Workshop on Circuits and Systems
in Karuizawa<\/th>\n		Karuizawa, Japan<\/th>\n<\/tr>\n
2-Mar-06<\/th>\nAdaptive Porting of Analog IPs with Reusable Conservative Properties<\/th>\nTakashi Nojima,
Shigetoshi Nakatake,
Toru Fujimura,
Koji Okazaki,
Yoji Kajitani,
Nobuto Ono<\/th>\n		ISVLSL06<\/th>\nKarlsruhe,
Germany<\/th>\n<\/tr>\n
2-Mar-06<\/th>\nMulti-SP: A Representation with United Rectangles for Analog Placement and Routing<\/th>\nNing Fu,
Shigetoshi Nakatake,
Mitsutoshi Mineshima<\/th>\n		ISVLSL06<\/th>\nKarlsruhe,
Germany<\/th>\n<\/tr>\n
2-Mar-06<\/th>\nFormulating the Empirical Strategies in Module Generation of Analog MOS Layout<\/th>\nTan Yan,
Takashi Nojima,
Shigetoshi Nakatake<\/th>\n		ISVLSL06<\/th>\nKarlsruhe,
Germany<\/th>\n<\/tr>\n
8-July-05<\/th>\nCAD Technology for LCD Design<\/th>\nTsuneo Munakata,
Kouji Yamaguchi,
Hideaki Chida<\/th>\n		AM-LCD ’05
pp327–pp330<\/th>\n		Kanazawa,
Japan<\/th>\n<\/tr>\n
18-Apr-05<\/th>\nThe Oct-Touched Tile: A New Architecture for Shape-Based Routing<\/th>\nNing Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani<\/th>\n		GLSVLSI 2005
P1.13<\/th>\n		Chicago,
USA<\/th>\n<\/tr>\n
Dec-04<\/th>\nAbstraction and Optimization of Consistent Floorplanning with Pillar Block Contraints<\/th>\nNing Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani<\/th>\n		IEICE TRANS.
FUNDAMENTALS,
VOL.E87-A, NO.12
pp.3224 — 3232<\/th>\n		Tokyo,
Japan<\/th>\n<\/tr>\n
Dec-04<\/th>\nA Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects<\/th>\nKeiji Kida,
Xiaoke Zhu,
Changwen Zhuang,
Yasuhiro Takashima,
Shigetoshi Nakatake<\/th>\n		IEICE TRANS.
FUNDAMENTALS,
VOL.E87-A, NO.12
pp.3258 — 3264<\/th>\n		Tokyo,
Japan<\/th>\n<\/tr>\n
Dec-04<\/th>\nA Device-Level Placement with Schema
Based Clusters in Analog IC Layouts<\/th>\n		Takashi Nojima,
Xiaoke Zhu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani<\/th>\n		IEICE TRANS.
FUNDAMENTALS,
VOL.E87-A, NO.12
pp.3301 — 3308<\/th>\n		Tokyo,
Japan<\/th>\n<\/tr>\n
26-Apr-04<\/th>\nA Device-Level Placement with Multi-Directional Convex Clustering<\/th>\nTakashi Nojima,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani<\/th>\n		GLSVLSI 2004
pp.196 — 201<\/th>\n		Boston,
USA<\/th>\n<\/tr>\n
29-Jan-04<\/th>\nMulti-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts<\/th>\nTakashi Nojima,
Xiaoke Zhu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani<\/th>\n		ASP-DAC 2004
pp.406 — 411<\/th>\n		Yokohama, Japan<\/th>\n<\/tr>\n
28-Nov-03<\/th>\n\u30a2\u30ca\u30ed\u30b0IC\u30ec\u30a4\u30a2\u30a6\u30c8\u8a2d\u8a08\u306b\u304a\u3051\u308b\u56de\u8def\u56f3\u30af\u30e9\u30b9\u30bf\u60c5\u5831\u306b\u57fa\u3065\u304f\u30de\u30eb\u30c1\u30ec\u30d9\u30eb \u914d\u7f6e\u624b\u6cd5\u306e\u63d0\u6848<\/th>\n\u91ce\u5cf6 \u9686\u5fd7,
\u6731 \u5c0f\u79d1, \u9ad8\u5cf6 \u5eb7\u88d5,
\u4e2d\u6b66 \u7e41\u5bff, \u68b6\u8c37 \u6d0b\u53f8<\/th>\n		\u30c7\u30b6\u30a4\u30f3\u30ac\u30a4\u30a2
\u96fb\u5b50\u60c5\u5831\u901a\u4fe1\u5b66\u4f1a
\u4fe1\u5b66\u6280\u5831
pp.193 — 198<\/th>\n		Kitakyushu, Japan<\/th>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/figure>\n<\/div><\/div>\n","protected":false},"excerpt":{"rendered":"

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