| Monday,
June 4th |
|
10am - 11am | Designing
for manufacturing variability with confidence | Texas
Instruments Dallas | Clive
Bittlestone Fellow |
|
2pm - 3pm | DFM Challenges
and Solutions for 65nm and below | TSMC
Taiwan | Y.K. Cheng Senior
Manager, DMP |
| 4:30-5:30pm
| Re-cap of SPIE paper on using model-based approach
to systematic variations | Qualcomm San Diego, CA
| Dan Perry Manager, DFM Implementation |
| Tuesday,
June 5th |
|
10am - 11am | Physical
and Electrical DFM: Critical Success Factors of 65nm and 45nm designs | STMicroelectronics
France | Raphael Bingert
Manager, DFM Enablement |
|
11am - noon | Context-specific
leakage and delay analysis of 65nm for lithography-induced variability | UMC
Taiwan | Dr. Chingchi
Yao Senior Director |
| 4pm
- 6pm | Special Executive
Briefing by Gary Smith |
| Wednesday,
June 6th |
| 11am
- noon | Process Friendly
Design Methodology for nanometer SoCs | STARC
Japan | Masami Murakata
Associate General Manager |
| 1pm
- 2pm | Design-Aware Photomask Inspection
| KLA-Tencor San Jose, CA | Venu
Vellanki, Senior Manager |
| 2pm
- 3pm | Physical DFM issues
and solutions for 65nm and below | Chartered
San Jose | B.P. Wong,
Director DFM Technologies |