| Date |
Title |
Editor |
school |
place |
| 27-Aug-09 |
A Fast Method to Analyze SRAM Fail Bit Count by Monte Carlo |
Shuhei Satoh,
Koutaro Hachiya,
Akio Nishida,
Shiro Kamohara |
IPSJ SIG Technical Report |
Tokyo,
Japan |
| 21-Apr-09 |
An Automatic Design Method for MOS Analog Circuits using Reduction of Independent Design Variables Based on Topological Constraints |
Katsuhiro Furukawa,
Yasuaki Inoue,
Saburo Hojyo |
Workshop on Circuits and Systems in Karuizawa |
Karuizawa,
Japan |
| 2-Mar-06 |
Adaptive Porting of Analog
IPs with Reusable Conservative Properties |
Takashi Nojima,
Shigetoshi Nakatake,
Toru Fujimura,
Koji Okazaki,
Yoji Kajitani,
Nobuto Ono |
ISVLSL06 |
Karlsruhe,
Germany |
| 2-Mar-06 |
Multi-SP: A Representation
with United Rectangles for Analog Placement and Routing |
Ning Fu,
Shigetoshi Nakatake, Mitsutoshi Mineshima |
ISVLSL06 |
Karlsruhe,
Germany |
| 2-Mar-06 |
Formulating the Empirical
Strategies in Module Generation of Analog MOS Layout |
Tan Yan,
Takashi Nojima,
Shigetoshi Nakatake |
ISVLSL06 |
Karlsruhe,
Germany |
| 8-July-05 |
CAD Technology for LCD Design
|
Tsuneo Munakata,
Kouji Yamaguchi,
Hideaki Chida |
AM-LCD '05
pp327--pp330
|
Kanazawa,
Japan |
| 18-Apr-05 |
The Oct-Touched Tile: A New Architecture for
Shape-Based Routing
|
Ning Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani
|
GLSVLSI 2005
P1.13
|
Chicago,
USA |
| Dec-04 |
Abstraction and Optimization of Consistent Floorplanning
with Pillar Block Contraints
|
Ning Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani
|
IEICE TRANS.
FUNDAMENTALS,
VOL.E87-A, NO.12
pp.3224 -- 3232
|
Tokyo,
Japan |
| Dec-04 |
A Fast Algorithm for Crosspoint Assignment under
Crosstalk Constraints with Shielding Effects
|
Keiji Kida,
Xiaoke Zhu,
Changwen Zhuang,
Yasuhiro Takashima,
Shigetoshi Nakatake
|
IEICE TRANS.
FUNDAMENTALS,
VOL.E87-A, NO.12
pp.3258 -- 3264
|
Tokyo,
Japan |
| Dec-04 |
A Device-Level Placement with Schema
Based Clusters in Analog IC Layouts
|
Takashi Nojima,
Xiaoke Zhu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani
|
IEICE TRANS.
FUNDAMENTALS,
VOL.E87-A, NO.12
pp.3301 -- 3308
|
Tokyo,
Japan |
| 26-Apr-04 |
A Device-Level Placement with Multi-Directional
Convex Clustering |
Takashi Nojima,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani |
GLSVLSI 2004
pp.196 -- 201 |
Boston,
USA |
| 29-Jan-04 |
Multi-Level Placement with Circuit
Schema Based Clustering in Analog IC Layouts |
Takashi Nojima,
Xiaoke Zhu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani |
ASP-DAC 2004
pp.406 -- 411 |
Yokohama, Japan |
| 28-Nov-03 |
Proposed Multilevel
Placement Method Based on Circuitry Cluster Information in Analog
IC Layout Design |
Takashi Nojima,
Sho-Ka Shu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani |
Design Gaia
The Institute of Electronics,
Information and Communication Engineers
Technical Report of IEICE
pp. 193 - 198
|
Kitakyushu, Japan |
