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Layout design

Analog / Custom LSI layout design platform

Improve both the quality and achieve a reduction of the design period through the re-use of the Takumi skill and the automation of the layout design, a coordination of the know-how of the designer and automation technology


  • Re-use based P&R
    • - Improve quality and shorten the design period with re-use based P&R
  • Constraint driven layout
    • - Reduce verification effort by the constraint-based layout tool
  • Analysis / Learning capability
    • - Reduce design time by following the optimal design procedures of the Takumi database
  • Improved editor functions
    • - Accelerate the design efficiency by the net-driven design environment with an increased degree of design
  • freedom
    • - Assist designers through flexible editing functions

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Layout Editor



In addition to polygon input, rule driven / net driven / constraint driven design approaches are also supported.

This flexibility allows the building of a highly scalable layout design environment.

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  • Supports large-scale data
  • (Stream 100 Gbyte, over 10 million net scale)
    • - Eliminated various restrictions such as the number of cells and the number of layers
    • - Industry-leading performance such as display, editing, data conversion
  • Fusion of polygon editing and net driven editing
    • - Rule-driven editing is possible by automatic equipotential line recognition and net tracing of polygon figures
    • - PushAside function of wiring, automatic loop elimination function
    • - Automatic net construction function at wiring input
  • Constraint-driven editing
    • - Layout editing function with circuit constraints
  • Flexible net driven
    • - Circuit changes can be reflected in the layout even when the circuit and the layout have different hierarchies
  • Intuitive and superior operability
    • - Multi-language support menu (Japanese mode, English mode, etc.)
    • - Windows-like operability
  • Easy customization
    • - Custom device generation by parameterized cell (ParaO)
    • - Provides customized environment with interpreted development language Axel
    • - Provides various functions such as database access, parameterized device definition (ParaO),
  • menu operation, verification, etc.
  • Distributed editing
    • - In order to design the same cell with more than one person, cells can be divided into regions (layered)
    • - Automatically generate a port at the disconnected part of the net and maintain the net driven data
    • - After completion of design, return to the original hierarchical structure and automatically maintains the net information
  • Extensive I/O
    • - EDIF Schematic, Spice netlist, Verilog-HDL
  • Support platform and database
    • - Supports Windows, RedHat Linux
    • - Mixed design environment that requires no data conversion between Windows and UNIX
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P2P Router



Interactive high-quality and high-speed automatic P2P router

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  • Supports efficient input
    • - Automatic routing between 2 points, Automatic bundle routing
    • - Effective auto finish function during manual wiring input
    • - Template based automatic routing using routing results
    • - Fly lines allow easy visualization of unconnected nets
    • - Routing line selection
    • - Rip up and re-route of selected nets

Hierarchy Rebuilder for Layout



Rebuild hierarchy of the netlist optimized for layout from the circuit hierarchy

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  • Without modifying the schematic, rebuild the layout visually to the optimum hierarchy
    • - Move, hierarchy extension, and hierarchy building of instances are possible while keeping connections
    • - Automatically generates netlist and port based on the built hierarchy
    • - Displays the result as a schematic image
    • - No need to generate schematic for layout
  • Supports flexible ECO (circuit change) function
  • Area calculation function
    • - Calculate area from circuit parameters at high speed
    • - List display, sorting function
  • Supports various netlist formats
    • - Spice, Verilog, CDL(LVS netlist), EDIF
    • - Inputs netlist directly from other schematic entry tools
    • - CDL, Spice, Verilog output

Constraint Driven Power Router



The world's first constraint-driven router to automatically generate wire slotting

  • Automatically generate resistance, shield, and impedance aware power slotting
  • Keep constraints after fine-tuning the wire width and path of the global and detailed routing phase
  • Early convergence at floor planning and top-level implementation
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Automatic Router



Shape-based high quality & high density router

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  • Using shape-based algorithm, allows high quality & high density results equivalent to manual wiring.
    • - Interactive automatic wiring on a net basis
    • - Specify layer, width, spacing in net units
    • - Multilayer support
    • - Enables smooth semiautomatic design by combining fully automated and interactive methods
    • - By designating the existing wiring as fixed or non-fixed, automatic wiring can be made incrementally
  • Provides dedicated routing options for memory, analog and LCD, etc.
  • Optional features for analog design
    • - Wiring length control
    • - Wiring resistance control
    • - Parallel wire length control
    • - Bus wiring
    • - Differential pair wiring
    • - Designation of wiring route
    • - Crosstalk control
    • - Star wiring
    • - Shield wiring
    • - Symmetry wiring

Block Level Compaction



High-speed interactive compactor for large scale data without net information

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  • High-speed compaction for block level and cell level wiring
  • High-speed JOG insertion
  • Executable also for polygon data
  • Partial compaction
  • Critical path display
  • De-compaction capability while keeping design rules

Interactive DRC/LVS



Reduces the final verification time by the sign-off tool


  • Highly accuracy Design Rule Checker for any angle design
  • Possible to execute for any specified area during layout
  • High-speed batch processing is possible such as array hierarchy processing
  • Extensive DRC verification functions: SPACE, WIDTH, ENC, INC, OVERLAP, various ELECT
  • Extensive options such as edge length and parallel line specification are prepared
  • Improve efficiency of verification by using logical operations at the same time
  • Real-time DRC that can be verified during layout design
  • Possible to define rule settings graphically by dedicated GUI
  • Equipped with the function to import rule files of other verification tools
  • Directly use the rule files of other verification tools
  • Mentor Calibre I/F: Integrated verification environment with Mentor Calibre
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  • Convert polygon data to net driven data
  • LVS verification can be performed with no connectivity information on the layout pattern
  • Device recognition function for special liquid crystal devices
  • Since the instance name and net name are displayed on the layout, easy to correct LVS error
  • LVS verification is possible by reading connectivity information directly from circuit data of Spice / CDL or Asca-Advanced
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High-speed and high-accuracy power supply analysis for power device



PowerVolt is a tool to provide analysis function for Power Devices. It works only with layout data and does not require preprocessing such as LVS. It has four major functionalities.

  • Statistic analysis for voltage, current and resistance of device.
  • Resistance distribution analysis.
  • Electrothermal analysis for Power device.
  • Transient analysis of Power device.
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