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Panel Layout Verification

Comprehensive verification features for FPD layout:
characteristic analysis in pixel cell, top level panel verification, etc.

  • High speed DRC/ERC/LVL verification with hierarchy process technology
    • Verifies entire array of the panel at high speed and high accuracy
  • 2D or 3D solver extracts parasitic resistance and capacitance in high accuracy
    • Extracts parasitic for both top panel wiring and pixel cell at high speed and high accuracy
  • Provides voltage drop analysis solutions for FPD

Interactive DRC/LVS tool



Reduces sign-off verification time

  • Provides easy to debug environment to modify layout
  • Real time DRC linked to layout editors
  • High accuracy DRC which allows any angle pattern verification
  • High speed array data verification with hierarchical processing
  • LVS enables to recognize particular kind of LC devices
  • GUI helps to create and edit design rule files
  • Imports rule files of third party verification tools
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LVL tool for FPD



Supports comparative verification of layout patterns

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  • Pattern comparison between specific layers
  • Pattern comparison between hierarchical cells
  • Compares hierarchical structure consistency
  • Easy to define rules
  • Supports hierarchical flattening process

ERC tool for FPD



Supports open & short checking of wiring

  • ・Verifies polygon patterns by equipotential line tracing approach
  • ・High-speed verification of pixel array by hierarchical processing
  • ・Powerful short path searching capability
  • ・Easy to define rules
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Resistance calculation tool for FPD



Automatically generates color filter substrate from product specification

  • Automatically generates color filter panel and color filter substrate
    • - Automatic placement of pixel photo spacer, transparent electrode and alignment layer
    • - Automatically generates seal figures
    • - Automatic placement of photo spacer and random cell
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Capacitance calculation tool for FPD



Industry's first panel-scale high accuracy and high speed capacitance extractor

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  • BEM (boundary element method) 3D capacitance extraction engine
  • Parasitic wiring extraction for panel with large scale and high-aspect ratio
    • - Generates extraction model with layout data and wiring cross section parameter
    • - Any angle and multilayer routing capability
    • - Supports non-flattening process
    • - Supports floating metal
  • Easy to check process structure and extraction results by 3D viewer

Resistance and capacitance calculation tool for FPD



Industry's first panel scale high accuracy and high speed resistance / capacitance extractor

  • High accuracy and high speed extraction with best suited algorithm for calculating resistance and capacitance
  • Parasitic extraction for large drawing and high aspect ratio panel wire
  • Extracted parasitic information helps circuit analysis
  • Applicable to characteristic analysis of various types of touch panels
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Voltage drop and current densities analysis tool for OLED display and OLED lighting



High speed and high accuracy IR drop verification for OLED display and OLED lighting

  • Displays the calculated result of the voltage drop and current density distribution of the wiring in the panel.
  • Calculates the current for each pixel and displays the current density by considering the voltage drop
  • Automatic recognition of wiring and devices
  • Device models
    • - Spice model (a-Si/LTPS TFT)
    • - Imports I-V characteristics (TFT / organic EL layer)
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