The industry standard layout design platform which seamlessly integrates each design approach; polygon, rule, net and constraint driven method Rule Driven Design > Reduces TAT more than 30% compared to polygon design   Layout design which keeps design rule     - Command operation speed is equal to polygon design     - With efficient wiring input editing capabilities, achieving the design speed which exceeds the polygon design     - Provides simple advance preparation environment, and flexibly work around the failure and/or modification of design rules     - Reduces verification time with real time DRC Net Driven Design > Reduces TAT to 1/3 compared to polygon design   Layout design which keeps design rule and net     - Efficiency of block level design exceeds rule driven method     - Achieves more design efficiency than other EDA vendors of chip level large scale data     - Possible to start design without netlist because the connection information can be easily made     - Enable to update design data with ECO function of netlist change     - Without modifying the schematic, possible to rebuild the layout hierarchy suitable for layout design     - Reduces verification process with real time LVS     - Enable to reuse polygon based design property by automatic generation of port and frame function Constraint Driven Design plus Automatic Layout > Reduces TAT to 1/5 compared to polygon design   Layout design which keeps design rule, net and constraint     - High quality automatic layout based on constraints     - Integrates manual editing and interactive automation tools     - High accuracy chip level estimation with high quality placement engine     - Making a database of circuit constraint and reuse     - With constraint verification function, preventing constraint violation Standardization   Link to other EDA vendors’tools     - Cadence Composer     - Mentor DAIC     - Mentor Calibre   Sharing with database of other EDA vendors     - Cadence Virtuoso   PDK     - Pcell I/F     - PyCell I/F   OA database support
Layout Editor  α-SX Ismo
Flexible and high speed design editor that supports mixed design approaches; polygon, rule, net and constraint driven design Supports large scale data, High speed data processing Equipping powerful wiring edit function Push Aside Bundle routing capability Automatic VIA switching Routing guidance Custom device generation by use of parameterized cell Intuitive and superior operability and easy customization Extensive I/O GDSII, OASIS, LEF/DEF EDIF Schematic, Spice netlist, Verilog-HDL Rule information of other EDA vendors
P2P Router  α-SX Pathmo
Interactive high quality and high speed automatic router Supports wiring input operation Automatic routing between 2 points, Automatic bundle routing Effective auto finish function during manual wiring input Template based automatic routing using routing results Efficient operation using fly line Routing line selection, Reshape routing shapes
Automatic Extraction & Verification of Design Constraint  α-SX Coulom
Prevent Layout design failure by constraint driven verification Automatically extracts layout constraint information from netlist Automatically extracts various constraints, symmetry, pair and current mirror, etc., and reflects them to CVM Automatic constraint generation based on user property Enables to customize extraction condition and extraction priority order Verifies consistency between constraint and layout before running LVS Improves layout design quality
Hierarchy Rebuilder  α-SX Hbuilder
With simple operation, rebuild the hierarchy suited for layout Without modifying the schematic, rebuild the optimum hierarchy to layout visually Move, hierarchy expansion, and hierarchy building of instances are possible while keeping connection Automatically generates netlist and port based on the built hierarchy Displays the result with schematic image No need to generate schematic for layout Supports flexibly ECO (circuit change) function Supports various netlists Spice, Verilog, CDL（LVS netlist）, EDIF Inputs netlist directly from other schematic entry tools CDL, Spice, Verilog output
Flow Control and Area Estimation  α-SX Bricks
High accuracy area estimation by automatic layout generation Control automatic tools; automatic device placer （Amper) and automatic constraint extractor （Coulom), etc. Estimates the area of all blocks together from the top to lower level Define target block to be estimated Define area value concerning the block which the circuit has not fixed Makes use of existing property as a hard block Easy to check each block area and device size by GUI
Analog Device Automatic Generator  α-SX Laplace
Automatic device generation by use of templates Reduces layout design period by use of template Symbolically-defined device placement location and routing rout on the template Easy to define placement location and routing rout by GUI Easy to lay out common centroid and repeat placement & routing of divided device Reduces library development period Applies to design reuse, such as process migration Automatic generation of macro library
Analog Device Automatic Placer  α-SX Amper
Sufficiently acceptable placement quality！ High quality and high speed automatic placement Placement quality which considers DC pass Automatic optimum size decision by the automatic adjustment function of device number of partitions, etc. Area optimization with automatic recognition of well electric potential Takes routing area into account Supports partial placement and interactive operation Supports CMOS, BiCMOS process
Automatic Router  α-SX Rexsir
Sufficiently acceptable routing quality！ High quality & high density shape based automatic router for block level and inter-block design Available for batch processing of entire wiring and/or partial wiring of layout Supports symmetry, differential pair, shield Control of the drawer wiring of Finger MOS Easy to define wiring prohibition area Multi ＶＩＡ, stacked ＶＩＡ Provides dedicated routing options for memory, analog and LCD, etc.
Analog compaction  α-SX Grana
Interactive device level compactor keeping design constraints Keeps place & Route constraint, symmetry and pair, etc. Partial compaction Compaction that takes account of well electrical potential Critical path display De-compaction capability to keep design rule
Inter-Block Compaction  α-SX Gravity
High speed interactive compactor for large scale data without net High speed compaction for inter-block and inter-cell wiring High speed JOG insertion Polygon data are also available Partial compaction Critical path display De-compaction capability to keep design rule
EM/IR Drop Verification  α-SX PowerVolt
High speed & high accuracy EM/IR Drop verification for power device and analog IC Interactive verification with built in high speed 2D solver Possible to verify with polygon data No need to invoke LVS/LPE （able to verify during design） Power device IR Drop analysis Analysis by defining current value or voltage value Device modeling using Spice model Analog IC EM/IR Drop analysis Analyze by use of simulation results
Interactive DRC/LVS/LPE  α-SX iDRC / iLVS / iLPE
Reduce sign-off verification time－verification・checking・correction at any time！ Debugging environment that makes easy to fix layout design Real time DRC that works together input and editing operations LPE enables to extract parameter from area routing and 45°routing data DRC possible to check any angle layout Easy to create and edit a design rule file using GUI Imports rules of other EDA vendors’ verification tool
Device TEG Automatic Generation Tool  α-SX TEGpert
Reduce device TEG development time to 1/10 or less Achieves 10X or more performance (automatic P&R process) in comparison with the efficiency of the other companies tools Applies easily to the next generation process and TEG spec modification Automatic generation of TEG generation specification document and measurement file Advance prevention of mask defect caused by human factor and wafer loss cost Supports generation and verification for developing the parameterized cell (ParaO) for new device
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