Total support for FPD layout verification: characteristic analysis in pixel cell, entire panel verification, etc.   High speed DRC/ERC/LVL verification with hierarchy process technology       Verifies whole array at high speed and high accuracy   2D or 3D solver extracts high accuracy parasitic resistance and capacitance       Extracts parasitic at high speed and high accuracy for both top panel routing and pixel cell   Provides voltage drop analysis solutions for FPD specific area
Interactive DRC/LVS  α-SX iDRC / iLVS
Reduces sign-off verification time Provides easy to debag environment to modify layout Real time DRC linked with layout editing High accuracy DRC which allows any pattern verification High speed array data verification with hierarchy processing LVS enable to recognize particular kind of LC device GUI helps to create and edit design rule files Rule files of third party verification tools can be imported
LVL for FPD  α-SX FineLVL
Supports comparative verification of layout patterns Pattern comparison between specific layers Pattern comparison of hierarchical cells Compares hierarchical structure matching Easy to define rules
ERC for FPD  α-SX FineERC
Supports open & short checking of wiring Verifies polygon patterns by equipotential line tracking approach High-speed verification for pixel array portion with hierarchical processing Powerful short path searching capability Easy to define rules
Resistance calculation for FPD  α-SX FineAcres
High speed & accuracy resistance extractor for complicated layout patterns High speed wiring resistance calculation with FDM (finite difference method) algorithm Complicated patterns including any angle, arc and slit are available Multilayer routing is available Measures resistance distribution for electrode with multipoint consecutive measurement method
Capacitance calculation for FPD  α-SX FineQap
Industry's first panel-scale high accuracy and high speed capacitance extractor BEM (boundary element method) 3D capacitance extraction engine Parasitic wiring extraction for panel with large scale and high aspect ratio Generates extraction model with layout data and wiring cross section parameter Any angle and multilayer routing capability Supports non-planarization process Supports floating metal Easy to check process structure and extraction results by 3D viewer
Resistance and capacitance calculation for FPD  α-SX FineResQ
Industry's first panel-scale high accuracy and high speed resistance & capacitance extractor High accuracy and high speed extraction using most appropriate algorithm for calculating resistance and capacitance value Complicated patterns including any angle, arc and slit are available Multilayer routing is available Parasitic wiring extraction for panel with large scale and high aspect ratio Generates extraction model with layout data and wiring cross section parameter Supports non-planarization process Supports floating metal Easy to check process structure and extraction results by 3D viewer Wiring parasitic information helps circuit analysis
IR drop verification for EL panel  α-SX FineVolt
High speed and high accuracy IR Drop verification for OLED Interactive verification including high speed 2D solver Supports polygon data Possible to verify data without LVS/LPE execution IR Drop analysis for OLED Analysis under conditions of specified current value or voltage value Device modeling using Spice model Anode / Cathode with resistance and consumption current of each pixel Calculates voltage drop of both sides Re-calculates consumption current of each pixels in consideration of voltage drop effect Analysis assistance Displays distribution of voltage drop / current density / power density
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