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FPD/fine-pattern design environment that greatly
reduces Turnaround Time for design
Key function
Handling of large and complex data
- Universally compatible binary database that can be used, as is,
with both Windows and UNIX.
Excellent user interface
- Windows-like operability
- Excellent operability which is fully optimized for keyboard,
mouse and tablet operation
- Multi language menus (Japanese and English modes)
Advanced editor
- Rule drive/Net driven design which reduce design mistakes
- Enable net driven editing from existing polygon data
- Push aside function which keeps design rule between polygon data
Perfect pattern editing commands
- Greatly reduce editing time by automatic router keeping consistent
resistance, bus function, trim function.
- Reduce verification time by various verification tool which is
specialized as FPD design.
Input of a wide variety of document information
- Dimension lines and schematic frames
Interactive conversion
- STREAM/DXF/IGES/GERBER(Laser,Fixed)
Support simultaneous optimization both pixel structure and driver circuit.
- Combine circuit analysis and optical analysis
| Alpha-SX Custom Design Platform |
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Key function of FineCreator
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Supported platforms
•Windows2000/XP •Sun/Solaris 8,9,10
•Red Hat Linux7.3/9
•Red Hat Enterprise Linux WS release 3,4,5.2
•Sun/Solaris X86 •SUSE Linux
Application design fields
•FPD
(TN/STN/a-TFT/LTPS/HTPS/PDP/OLED/electronic paper...)
•All fine-pattern design fields (such as Color-filters,magnetic
heads,BGA,TAB,LeadFrames,light gides,sensors, and
thermal heads) |
| FineArts Fine-pattern design package |
•Generation of special-figure patterns
(arched ellipses, cams, convolutions, 8-segments figures)
•Additional-line input
•Bundling and trimming
•Automatic equivalent resistance routing
•Wiring resistance adjustment
•Surface generation
•Reports (resistance, area calculation, etc.)
•Schematic frame placement and dimension-line input
•Comment input |
| FineLVL Layout vs. Layout checker |
FineERC Short and floating checks |
| The layout pattern between two cells is comparing verified.
Comparing only the difference figures of hierarchical cell
enables very high-speed performance. |
High speed verification of short and floating between
polygon figures which are not associated with connectivity
information. |
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| FineAcres High accuracy resistance calculator |
FineQap 3Dimensional capacitance extractor |
•The interconnect resistance of the complex shape composed
of any-angle and the arc can be calculated in high-speed
and high accuracy. This product is using the finite difference
method algorithm.
•Supporting multi layer wiring
•Analysis of resistance distribution by multipoint sequential
measurements function |
•Extract 3D parasitic capacitance by boundary element
method and 3D capacitance extractor engine.
•Parasitic extraction for interconnect of large size drawing and
high aspect ratio panel
•Easy generation of extracting model from layout data and
cross section parameter
•Support both any angle wire and multiple layer wire |
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| FineGFP Glass floor planning |
FineRFP Reticle desing and verification |
Greatly reduce the trade off time for the best selection of
multiple surfaces configuration.
•Generation of glass board design from base shot data, reticle(mask),
generation parameters.
Report the number of shots and reticle information
Generat Glass substrate cells and reticle cells |
•Shot cells design function which are placed on reticle.(Large size panel)
Divides the panel design into reticle patterns
Places patch patterns on the division line
Reports reticle informations, the shot and the alignment mark coordinate
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| FineCFC Design the color filter |
Design color filter substrate parametrically
•Place alignment layer elements, transparent electrode elements,
photo spacer elements and seal elements
•Support both color filter panel and color filter substrate designing |
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| FineFPC Design around FPC and COG |
•Generation of cells for IC and FPC and build connectivity information
between those cells by using port information(CSV format)
•Calculate wire width which resistance value matches to the rule
file(CSV format) and verify the resultant resistance value.
•Footprint wiring capability which bundles multiple same net ports.
•High accuracy interconnect resistance calculation linked with 3D
extractor FineAcres. |
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FPD panel Circuit design & Optical simulation design environment
| Schematic Entry |
| Schematic entry which corresponds to layout design, LVS verification and circuit simulation etc. |
•Support of 2D array instance for pixel array structure definition
•Parametric modeling for parasitic effect of interconnect |
•Power mesh model definition for IR drop
analysis
•Back annotation of interconnect parasitic
information from FineAcres and FineQap. |
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| Panel circuit simulation I/F |
| Analysis of accumulated Pixel capacitance |
•3D RC extractor for Pixel device *1
•Circuit simulation with 3D interconnect parasitic effect |
•N e t l i s t r e d u c t i o n o f a r r a y
structure circuit (WLModeler)
•Simulation of driver circuit with
the load depends on panel size
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| *1:Use ExperLCD |
| SimfaceLCD Simulation I/F for pixel device characteristic |
| Trade off design using dynamic optical analysis with liquid crystal molecule behavior. |
•Generate a table circuit model of the LC that consist of voltage
dependent capacitance and dynamic characteristics of LC.
•Transient optical simulation with simulated wave forms. *2 |
•Concurrent simulation with circuit simulator and LC numerical
solver.(Under development)
•Usable of existing circuit simulator model |
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| *2:Use ExperLCD |
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