Accurately simulate dishing effect of Cu wire resistance increase

Evaluate planarity of chip layout after CMP

With rapid advancement of semiconductor technologies, DFM (Design for Manufacturability) has become increasingly important. CMP-Designer is a DFM tool, which will simulate CMP (Chemical Mechanical Polishing) process to help chip layout design improve planarity hampered by non-uniformity of metal density or film thickness. CMP-Designer has been already adopted by leading semiconductor companies, which are trying to establish production lines of nanometer-scale process node beyond 90 nm, and have been in practical use, because of its accuracy and flexibility to be applied to variety of process options. CMP-Designer has 3 versions: SimCu for copper interconnect, SimSTI for STI (Shallow Trench Isolation), and SimILD for ILD (Inter- Layer Dielectric). SimCu complies with 45 nm process node and beyond.

Features

Physics based Model
The simulator is based on a model by stress-strain relation, with Pad deformation being formulated by the stress response function. High simulation speed is realized by FFT (Fast Fourier Transform) and improved numerical analysis algorithm.
COG Model
Accurate dishing and erosion are calculated with an original model, COG (Copper Global) model, where Dishing and Erosion are modeled as having mutual interaction with the two being connected by a spring. COG model can handle dishing dependence on Cu wire width.
Multi-layer Cu wire
Dishing and erosion of each multi copper layers are simulated after each metallization process, taking the roughness or topography of under-layers into consideration with no limitation of number of metal and/or isolation layers.
ECP Model
ECP (Electroplating) model is integrated to simulate Copper thickness with consideration of Over-fill/Super-fill as well as Conformal-fill.
Slurry Model
It can handle such slurry as Ceria, whose abrasive rate is not proportional to applied pressure (non-Preston), as well as Preston slurries.
Film Formation Model
It can handle deposition of various films, such as CVD (Chemical Vapor Deposition), HDP (High Density Plasma), and reflow film.
Total Full-chip LSI Simulation
It can handle various process steps of LSI’s in full-chip, such as STI, PMD (Pre-Metal Dielectric), and multi-layer copper and/or aluminum wires as total CMP simulation for evaluating its planarity.

Calibration Support Service

In addition to providing the CMP simulator, JEDAT has rich support knowledge and know-how on fitting parameters to maximize accuracy, calibrating those physical parameters with measured data. With these models and fitting, CMP-Designer claims high simulation accuracy of within 5% discrepancy against measurement in Multi-layer Cu wire simulation.

How to apply CMP-Designer in your process development

CMP-Designer is primarily introduced and adopted in R & D of nanometer-scale wafer process for optimizing Cu and STI process and materials(e.g., slurry with proper characteristics), but is now expanding its application to be used in LSI design for chip layout optimization by dummy fill for yield and performance improvement in production lines, being integrated into customers’ DFM system environment.
CMP-Designer has Alpha-SX(Custom LSI design tool) and HotScope(DFM Viewer) interface with its GUI as well as core modules of simulation and density calculation. An extreme high speed density calculator (DFRAME) calculates not only wire density but also extracts wire width from hierarchical layout data (GDSII) for CMP simulation.
DFM system example, integrating CMP-Designer, shows that dishing data by CMP simulator is interfaced to LPE (Layout Parasitic Extraction) so as to perform accurate post-layout simulation with the effect of Cu wire resistance increase by dishing.

Support OS : RedHat Linux, SUSE Linux, Windows 2000/XP

DFM System Example

*CMP-Designer is a Trade Mark of Semiconductor Leading Edge Technologies, Inc. (Selete)

Cu-CMP Simulation Compared with Measurements