Circuit design and debugging environment for ICs and FPDs

	Schematic entry and editing	Debugging environment based on cross-probing
	Simulation analysis condition setting	Verification result back-annotation

Features

• Seamless integration with IC and FPD layout design environment
• User-friendly design entry environments from the behavior level to the transistor level
• Efficient reference and debugging environments for multi-hierarchy, large-scale schematics
• Supports easy interfacing with de-facto simulators
• Efficient debugging environment based on cross-probing with simulation results
• Implement setting up, saving, and reusing analysis conditions based on simulation control
• Coexistence design environment of both Windows/Unix

Powerful schematic debugging environment

• Dynamic search for rule check results including net schematics
• Dynamic signal navigation and automatic generation of navigated schematics
• Net browser display and netlist output specified by leaf views
• Coexistence environment of both Windows/Unix

Environment supporting interface with layout design

• Cross-probing between expanded layout data and schematic view
• Block generation and netlist output based on 2D array instance definitions

Easy-to-use customization environment

• GUI customization, database access, and development of unique editing commands
• Interface with simulation and layout design based on parameterized instances

Newly added functions of AscaSimfaceAsca

Signal navigator

• Specification of pins and nets on a schematic and back-and-forth navigation of nets
• Specification of pins on an intermediate block and navigation of the parent block on which the pins are referenced

Schematic generation

• Automatic generation of schematic from a netlist with LPE results
• Automatic generation of the schematic for a layout hierarchy from a logic schematic

View control

• Automatic control of hierarchical structures for each export target (such as Verilog, SPICE, and CDL)
• Display of tree-format hierarchical structures for each Verilog, Analog, and CDL; metal option; etc.

Symbol generation

• Automatic generation of symbols from module definitions of SPICE and Verilog.

Other functions

2D array instance function

• Automatic generation of SPICE, CDL, layout from instance name based 2D definitions
• Definition of TFT pixel array structures

Editing function

• Net browser specified by leaf views
• Switching of metal option schematics
• Editing-in-place of hierarchical blocks
• Support of parameterized instances

Coulom connection

• Display, editing, and saving of analog device constraints to a database

Import & Export

• EDIF Schematic
• SPICE Export
• LVS-SPICE Export
• Verilog-HDL Export
• SPICE/DSPF Import

Specification of analysis control statements in compliance with HSPICE

GUI-based easy option setting

Setting based on specification of signals on a schematic or instances

• Setting of schematics in blocks of the same type but having different paths

Setup of ting up independent voltage/current sources based on virtual symbols

Cross-probing between schematics and waveform views

Ultrahigh-speed netlist generation

Easy integration with user simulators

• Powerful customization environment

Design Flow

- Signal navigator -		- CVM(Constrains View Manager) -