Next-generation analog LSI design environment

Designers of analog LSI are required to consider process variability, parasitic parameters, and trade-offs between performance and stability. To date, it has not been possible to automate analog design. Almost all design processes, from the basic circuits to layouts, are done manually.
Alpha-SX/AnalogCreator is a design environment that provides tools for circuit debugging, automatic design constraint extraction, automatic analog device layout generation, parasitic parameter extraction, and debugging. It supports analog LSI design consistently.
This software lets you undertake and solve a wide range of layout problems, thus improving design efficiency and reducing the time needed to complete a design.

Key Features

○ Circuit and layout design environment

Circuit data and layout data are managed in an integrated manner to allow them to be used together.

○ Automatic layout generation

The layout of an analog device is automated by utilizing optimized pair devices, placement, routing, and compactors.

○ Constraint extraction and management

Automatic extraction of constraints from circuits; these extracted constraints can then be observed during layout tool control.

○ Back-annotation

Environments are supported to enable simulation, extraction, and back-annotation in the design of both circuits and layouts; this is truly a next-generation analog device design environment.

Design Flow

Floor planner Proton

Device synthesis Laplace

AnalogCreator comprises the following tools.

■ Specifications & constraints analysis
"SpiceQuest"

□ Target specifications and circuit constraints analysis

□ Test bench generation

■ Circuit design
"Asca"

□ Hybrid Windows/UNIX design environment

□ Powerful editing(enabling semi-automatic routing, editing-in-place, etc.)

□ Same user interface for both circuit design and layout design

□ Easy customization (GUI and command incorporation)

□ Can be interfaced with de-facto simulators

□ Cross-probing between schematics and waveform views

■ Layout prototyping
"Dessin"

□ Dessin offers users the ability to obtain symbolic image of layout by prototyping in the phase of circuit design.

□ Parasitic RC extraction

■ Automatic layout constraint extraction
"Coulom"

□ Setup of rules for constraint extraction

□ Automatic extraction: Symmetry Automatic extraction of targets from a circuit topology

□ Automatic extraction: Group Extraction of a group of devices that are highly dependent on one another

□ Automatic extraction: Pair Extraction of current mirrors

□ Support of manual addition (routing and guard ring) and modification of constraints

□ Generation of a database of constraints according to circuit type

■ Analog block prototyping
"Mosla"

□ User can extract constraints from a schematic by one-button automatically, and generate a layout image instantly.

■ Hierarchy Builder
"Hbuilder"

□ Hbuilder can rebuild the circuit hierarchy for layout from the one for simulation.

■ Task control and chip size estimation
"Bricks"

□ Controlling the iteration of tools and managing the design status

□ Hierarchical chip size estimation

■ Floor planner
"Proton"

□ Early estimation of chip size and layout image by allocating devices to mesh unit of floorpplan.

■ Device synthesis
"Laplace"

□ Device synthesis Laplace

□ Specification of generation templates and parameters

□ Selection of devices according to circuit and layout and corresponding modification of parameters

□ Generation of a device on a common centroid according to constraints

■ Automatic placement
"Amper"

□ Implementation of a device that satisfies the area and routing length requirements at or in excess of a manually achieved level by taking relative locations on the schematic into account and by using the Multi-Directional convex clustering method

□ Automatic selection of optimum patterns (R, C, and TR) for a layout from multiple device parameter candidates

□ Automatic placement based on layout and parasitic constraints

■ Automatic routing
"Rexsir"

□ Pair routing, equi-length routing, and shield routing necessary for analog device design

□ Support of devices, cells, and blocks

□ Interactive editor for automatic routing

■ Analog compaction
"Grana"

□ Compaction that maintains conformance to analog device constraints

□ Compaction that maintains conformance to symmetry constraints in routing

■ Parasitic parameter extraction/debugging environments
"iLPE and iLVS"

□ Enabling polygon data to be processed, in conjunction with iLVS

□ Support of AREA routing and 45-degree routing

□ Extraction of device parameters and device parasitic parameters

□ Back-annotation of LPE outputs on Asca

□ Cross-probing of parasitic information between circuit data and layout data