Amper extensively reduces TAT of the layout design by abundant constraints assigned by designer and its partial placement functions.

Amper is the high speed device placer by controlling the layout data abstractly. By processing the layout data in abstract ways, routing area will be estimated so that the optimum layout for both the placement and routing will be achieved.
This tool is interactively operated by Alpha-SX and all of the devices such as MOS, BJT, resistance, capacitance that are handled in Alpha-SX can be placed. Also, the placement per block, grouped elements can be done so this tool is available for the extensive area of design environment including both Analog and Digital design environment.
Rich and powerful constraints can be automatically extracted from the editor, and interactively modified. Also, conducting the manual placement and auto placement (auto partial placement) interactively, placement with highest quality considering the details of characteristics will be promised.
By employing the optional batch process, elements can be separated and placed automatically to satisfy the constraints while checking each placement result as the element figure changes.

Prime features of Amper

MOS/BJT, Analog / Digital supported
High speed processing by abstract data control
Placement by estimating the routing area by global routing
Auto mirror, rotation for element
Auto packing of MOS transistors
Partial placement
Group placement
Auto extraction of constraints
Rich constraints
Auto element figure deformation and execution

High speed placement with the high quality

Amper accomplishes the optimum placement with the best quality by controlling the layout information in abstract ways. Since it is hard to say the layout with minimum area size always equals to the most optimum solution for the routing and placement, Amper evaluates the placement precisely by controlling the placement and routing in abstract way. Also, loads of manual editing after the placement will be reduced extensively by applying mirror and rotation to elements and packing of MOS transistors. Moreover, the layout with the highest quality will be promised by applying the various types of placement constraint.

Flexible assignment of constraints supported

Specifying the placement area, elements
Space constraint
Symmetry constraint
Group constraint
Align constraint
Site constraint
Graphical set up of constraints

Design integrity

Amper’s automatic is integrated with net driven interactive bench environment. By integrating with rich design environment of Alpha-SX and other related tools (REXSIR, GRAVITY, LAYVER) interactively, TAT will be extensively reduced for the layout design.

Automatic Element Figure Deformation

Partial placement

Since the specific devices on the circuit can be placed area by area, the partial modification of the placement can be done and the placement can be processed in units of group, area. Automatic placement can be executed interactively with the manual operation such as the insertion of guard rings, change of element figures and partial routings.

Auto extraction of constraints

By extracting constraints automatically from the parameters, connectivity between the elements and relative position of the elements on the schematic floor, the time for setting up the constraint will be extensively reduced. And the constraints can be appended/changed easily to reflect the designer’s intent more precisely.

Automatic element figure deformation

The layout will be largely different according to the element figures. Generally, element figures will be decided according to the designers’ experience. AMPER supports the trials of the placement by each different element figure. It is possible for designers to achieve the most optimum element figures by checking each layout result as the element figure changes.