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A New-generation Integrated Design Environment for the Area of Semiconductor and Fine-pattern Design
Alpha-SX is the latest offering in Jedat's SX series of electronic design automation (EDA) software. This new-generation software draws on the many years of experience and expertise gained by the SX-9000 system, and pools together the very latest technology resulting from extensive R&D in collaboration with industry and academic circles.
Alpha-SX is fully equipped with the schematic editor "Asca" and layout editor "Ismo" as its core tools and supports a substantial range of editor options, verification tools and automating tools exclusively for the fine-pattern designs such as liquid crystal display(LCD). It is also provided with I/Os for various industry standard external formats, and supports data output to masking systems, plot output and other special formats. In addition, Alpha-SX lines up “Development Kit" that provides a programming interface for customers to develop their own design environments. Customers can also commission Jedat's specially appointed Custom Development Department to develop custom software.
Alpha-SX allows the customer to build an integrated design environment that brings together circuit and layout design environments, and provides a new, constraint-driven design environment and design methodology by CVM, the constraint mechanism Manager.
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| Main Product Components |
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- Basic System, Editor Options
- Asca
"Schematic entry with powerful circuit debugging functions"
This is the basic system on which circuit design is performed. This integrated design environment incorporates a powerful range of functions including schematic entry, interfacing with various circuit simulators, waveform analysis viewer, and signal navigation, to mention but a few.
- SimFaceA
"Simulation interface"
This simulation controller controls setting and execution of circuit simulator analysis conditions. It can be interfaced with various third-party simulators.
- SpiceChart
"Waveform analysis viewer"
This analysis viewer is for viewing simulation results. Functions such as cross-probing with schematics help build a powerful debugging environment.
- WLModeler
"Wire load modeler"
This tool places dedicated symbols in schematics as wire loads to model wiring parasitic effects.
- Dessin
"Physical image planner"
This simplified floor planner uses symbols to design floor plans at the circuit design stage. It allows the customer to evaluate routing delays, for example, at the initial stages of design and perform forward annotation to layout design.
- Ismo
"New-generation advanced layout system"
This is the basic system on which layout design is performed. Ismo functions as an integrated layout design environment that supports large-scale, high-integration and high-performance semiconductors. It is provided with polygon, rule-driven, net-driven, and constraint-driven design modes for specific design targets. Also, automatic placement, automatic routing, verification, and other functions are integrated and implemented on a high-speed, advanced and highly operable manual design environment.
- FineArts
"Editor option for fine-patterns"
This editor option is exclusively for fine-patterns, and supports input of special-figure patterns (arched ellipses, cams, convolutions, 8-segment figures, etc.), pixel panel input, bundling input, trimming, automatic equivalent resistance routing, surface generation, schematic frame placement, dimension-line input, comment input, and other functions.
- FineRFP
"Reticle floor planner"
This reticle floor planner is exclusively for FPDs(Flat panel displays). It enables design of floor plans by shot division of panel layouts and output of recipe information for exposure.
- Automating Tools
- Coulom
"Automatic constraint extractor"
This tool automatically extracts the various constraint information needed for designing layouts, such as symmetrical parts of circuits, element groups having high group dependency, and pairs and current mirrors, from the circuit topology information on the schematic. These constraint conditions can be customized, which means that environments matched to individual design targets can be flexibly built.
- Proton
"Floor plan generator"
This is a floor planning environment for layouts. By allocating and placing symbols on a highly operable mesh, various floor plans can be efficiently compared and evaluated while taking into consideration constraints unique to analog design at the initial stage of the design process.
- Laplace
"Device and cell generator"
This environment is for automatically generating device and cell layouts. It uses templates to enable flexible control of placement and routing of MOSFETs having a large width unique to analog design, and modules such as resistors and capacitors that must be placed in pairs. It adopts a dedicated GUI comprising symbolic element placement and mesh-type routing. This enables batch-generation of multiple devices and cells having different parameters and reuse of design parameters.
- Amper
"Interactive high-speed automatic device placer"
This tool places MOSFETs, BJTs, resistors, capacitors, and other devices at high speed in accordance with constraint conditions including oppositional constraints, symmetry specification and group specification. Placement and routing are expressed abstractly. This enables placement including wire lengths and wire areas between elements to be accurately evaluated to obtain high-quality placement results.
- Rexcell
"Automatic placement for custom design"
This automatic placement tool is exclusively for analog mixed signal ICs. This tool is set at a more affordable price than products intended for large-scale digital LSI.
- Rexsir
"High-density automatic router"
This tool employs shape-based routing to perform routing between MOS/Bipolar devices and blocks at the same quality and density as in manual design. Just like other tools, Rexsir can be executed interactively from Ismo, which means that the optimum layout can be completed in a shorter turn around time when used in conjunction with manual layout design.
- Grana
"Layout compactor"
This tool is a layout optimizing environment for compacting layouts with placement of symmetry, pairs, etc. and routing constraints held intact. Compaction results as the designer intended can be obtained since this tool allows compaction of not just entire layouts but also specified areas of layouts, too.
- Verification
- iDRC/ERC
"Interactive DRC/ERC"
- iLVS
"Interactive LVS"
- iLPE
"Interactive parameter extractor"
iLPE provides layout verification tools such as DRC (Design Rule Check)/ERC (Electrical Rule Check), LVS (Layout .vs. Schematic), LPE (Layout Parameter Extract) that can be executed interactively from Ismo.
- FineERC
"Interactive Fine ERC"
This interactive ERC (Electrical Rule Check) is exclusively for fine-patterns such as in liquid crystals, and verifies shorts and floats between figures that have no connection information.
- FineLVL
"Interactive Fine LVL"
This interactive LVL (Layout .vs. Layout) checker is exclusively for fine-patterns such as in liquid crystals and compares and verifies figure differences between the layout patterns of two cells.
- FineAcres
"High-accuracy resistance calculator"
This high-accuracy resistance calculator tool uses algorithms incorporating the finite difference method (FDM) to calculate the routing resistance value of complex shapes that contain any angle polygons or arcs at high speed.
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