Alpha-SX Ver. 3.3.0 has been released. This release includes the following enhancements, the primary purpose of which is to improve performance and support large-scale data:
Ismo
Improved performance of cross probe between Asca and Ismo
Enhanced net-driven function
Enhanced placement and editing function of standard cell in rows
ParaO, handling of more complex process constraints by supporting VIA
Placement function of the bitmap data on layout
Template-based bus wiring function (Pathmo)
Asca
Net information comparison function
Integrated GUI for Verilog input and output
Parameter passing function
Invoking function of third party waveform viewers
Hbuilder (hierarchy building tool)
Inherited constraints (cluster, pair constraint…) in hierarchy editing
Preview function (automatic generation of hierarchical structured circuit)
Enhanced passing parameter function
Enhanced cross probe function
Structure checking function for converted net list
Loading function from the existing layout
Physical verification (iDRC, iLVS)
Enhanced rule analysis function
Improved rule conversion performance of third party tools
AnalogCreator
Area estimating function of the entire hierarchy (Bricks) released
Layout synthesis (Laplace), handling of multi- transistor patterns
Device automatic placement (Amper), interactive automatic placement function
Floor plan constraint (CVM), input and output function of excel format
FineCreator
LCD simulator (ExpertLCD) interface (SimfaceLC) released
Automatic generation tool of IC-FPC routing (FineFPC) released
Automatic generation tool of exposure recipe for FPD (FineGlass) released
FineAcres, logical calculation function and property setting function
FincERC, data processing function of hierarchical array layout data
Contact point for technical inquiries:
Alpha-SX e-mail:
Hotline (direct):+81-3-5847-0318/+81-50-5555-5604 (IP telephone)
Sales inquiries:
Tokyo sales: +81-3-5847-0313/+81-50-5555-5603 (IP telephone)
Osaka sales: +81-6-6150-0930